IS42S32200C1-6TL ISSI, Integrated Silicon Solution Inc, IS42S32200C1-6TL Datasheet
IS42S32200C1-6TL
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IS42S32200C1-6TL Summary of contents
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... Rev. B 1/18/07 JANUARY 2007 OVERVIEW ISSI 's 64Mb Synchronous DRAM IS42S32200C1 is organized as 524,288 bits x 32-bit x 4-bank for improved performance. The synchronous DRAMs achieve high- speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. ...
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... IS42S32200C1 GENERAL DESCRIPTION The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 2,048 rows by 256 columns by 32 bits. The 64Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode ...
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... IS42S32200C1 PIN CONFIGURATIONS 86 pin TSOP - Type II for x32 V DD DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM0 WE CAS RAS CS NC BA0 BA1 A10 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 V DD PIN DESCRIPTIONS A0-A10 Row Address Input A0-A7 ...
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... IS42S32200C1 PIN CONFIGURATION PACKAGE CODE BALL FBGA (Top View) (8. 13.00 mm Body, 0.8 mm Ball Pitch PIN DESCRIPTIONS A0-A10 Row Address Input A0-A7 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ31 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select ...
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... IS42S32200C1 PIN FUNCTIONS Symbol Pin No. (TSOP) Type A0-A10 Input Pin BA0, BA1 22,23 Input Pin CAS 18 Input Pin CKE 67 Input Pin CLK 68 Input Pin CS 20 Input Pin DQ0 10,11,13 DQ Pin DQ31 74,76,77,79,80,82,83,85 45,47,48,50,51,53,54,56 31,33,34,36,37,39,40,42 DQM0 16,28,59,71 Input Pin DQM3 RAS 19 Input Pin ...
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... IS42S32200C1 FUNCTION (In Detail) A0-A10 are address inputs sampled during the ACTIVE (row-address A0-A10) and READ/WRITE command (A0-A7 with A10 defining auto PRECHARGE). A10 is sampled during a PRECHARGE command to determine if all banks are to be PRECHARGED (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command ...
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... IS42S32200C1 enabled or disabled. AUTO PRECHARGE does not apply except in full-page burst mode. Upon completion of the READ or WRITE burst, a precharge of the bank/row that is addressed is automatically performed. AUTO REFRESH COMMAND This command executes the AUTO REFRESH operation. The row address and bank to be refreshed are automatically generated during this operation ...
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... IS42S32200C1 TRUTH TABLE – COMMANDS AND DQM OPERATION FUNCTION COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank/column, start READ burst) WRITE (Select bank/column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH ...
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... IS42S32200C1 (1-4) TRUTH TABLE – CKE CURRENT STATE COMMANDn Power-Down X Self Refresh X Clock Suspend X (5) Power-Down COMMAND INHIBIT or NOP (6) Self Refresh COMMAND INHIBIT or NOP (7) Clock Suspend X All Banks Idle COMMAND INHIBIT or NOP All Banks Idle AUTO REFRESH Reading or Writing VALID See TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n NOTES: 1. CKEn is the logic state of CKE at clock edge n ...
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... IS42S32200C1 NOTE: 1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table - CKE) and after t previous state was SELF REFRESH). 2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state ...
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... IS42S32200C1 TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK m CURRENT STATE COMMAND (ACTION) Any COMMAND INHIBIT (NOP/Continue previous operation) NO OPERATION (NOP/Continue previous operation) Idle Any Command Otherwise Allowed to Bank m Row ACTIVE (Select and activate row) Activating, READ (Select column and start READ burst) ...
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... IS42S32200C1 7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been inter- rupted by bank m’s burst. ...
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... IS42S32200C1 FUNCTIONAL DESCRIPTION The 64Mb SDRAMs 512K banks) are quad-bank DRAMs which operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 2,048 rows by 256 columns by 32bits. Read and write accesses to the SDRAM are burst oriented; ...
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... IS42S32200C1 REGISTER DEFINITION Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS\ latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION. The mode register is programmed via the LOAD MODE ...
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... IS42S32200C1 Burst Length Read and write accesses to the SDRAM are burst ori- ented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length determines the maximum number of column loca- tions that can be accessed for a given READ or WRITE command. Burst lengths locations are ...
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... IS42S32200C1 CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge ...
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... IS42S32200C1 OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Activating Specific Row Within Specific Bank). ...
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... IS42S32200C1 READS READ bursts are initiated with a READ command, as shown in the READ COMMAND diagram. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst ...
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... IS42S32200C1 same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in the READ to PRECHARGE diagram for each possible CAS latency; data element either the last of a burst of four or the last desired of a longer burst ...
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... IS42S32200C1 Consecutive READ Bursts T0 CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - NOP NOP NOP READ BANK, COL n+1 D OUT OUT NOP NOP READ BANK, COL n+1 OUT OUT Integrated Silicon Solution, Inc. — www.issi.com — ...
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... IS42S32200C1 Random READ Accesses T0 CLK COMMAND READ BANK, ADDRESS COL CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com — Rev. B 1/18/ READ READ READ BANK, BANK, BANK, COL b COL m COL OUT OUT CAS Latency - 2 ...
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... IS42S32200C1 RW1 - READ to WRITE CLK DQM COMMAND ADDRESS DQ RW2 - READ to WRITE With Extra Clock Cycle T0 CLK DQM COMMAND READ BANK, ADDRESS COL READ NOP NOP NOP BANK, COL n D CAS Lantency NOP NOP NOP OUT CAS Lantency 3 Integrated Silicon Solution, Inc. — www.issi.com — ...
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... IS42S32200C1 READ to PRECHARGE T0 T1 CLK COMMAND READ NOP BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com — Rev. B 1/18/ NOP NOP NOP PRECHARGE cycle BANK (a or all) ...
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... IS42S32200C1 READ Burst Termination T0 CLK COMMAND READ BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - BURST NOP NOP NOP TERMINATE n+1 D OUT OUT BURST NOP NOP TERMINATE cycles n+1 OUT OUT Integrated Silicon Solution, Inc. — www.issi.com — ...
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... IS42S32200C1 WRITEs WRITE bursts are initiated with a WRITE command, as shown in WRITE Command diagram. WRITE Command CLK HIGH - Z CKE CS RAS CAS WE A0-A7 COLUMN ADDRESS A8, A9 AUTO PRECHARGE A10 NO PRECHARGE BA0, BA1 BANK ADDRESS The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access ...
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... IS42S32200C1 WRITE Burst CLK COMMAND ADDRESS Burst length = 2 DQM ix low. WRITE to WRITE COMMAND DQMx is low. Each Write Command may be to any bank. Random WRITE Cycles CLK COMMAND ADDRESS DQMx is low. Each Write Command may be to any bank WRITE NOP NOP BANK, ...
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... IS42S32200C1 WRITE to READ T0 CLK COMMAND WRITE BANK, ADDRESS COL WRITE to PRECHARGE ( CLK DQM COMMAND WRITE BANK a, ADDRESS COL Integrated Silicon Solution, Inc. — www.issi.com — Rev. B 1/18/ NOP READ NOP BANK, COL CLK ( NOP NOP NOP PRECHARGE BANK (a or all) ...
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... IS42S32200C1 WRITE to PRECHARGE ( CLK DQM WRITE COMMAND BANK a, ADDRESS COL WRITE Burst Termination COMMAND ADDRESS 28 2 CLK ( NOP NOP NOP PRECHARGE BANK (a or all n CLK BURST WRITE TERMINATE BANK, (ADDRESS) COL DON'T CARE Integrated Silicon Solution, Inc. — www.issi.com — NOP ...
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... IS42S32200C1 PRECHARGE The PRECHARGE command (see figure) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (t the PRECHARGE command is issued. Input A10 deter- mines whether one or all banks are to be precharged, and in the case where only one bank precharged, inputs BA0, BA1 select the bank ...
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... IS42S32200C1 CLOCK SUSPEND Clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. ...
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... IS42S32200C1 BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation ( ...
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... IS42S32200C1 WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after t where t begins when the READ to bank m is registered. ...
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... IS42S32200C1 ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage DD MAX V Maximum Supply Voltage for Output Buffer DDQ MAX V Input Voltage IN V Output Voltage OUT P Allowable Power Dissipation D MAX I Output Shorted Current CS T Operating Temperature OPR T Storage Temperature STG DC RECOMMENDED OPERATING CONDITIONS ...
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... IS42S32200C1 DC ELECTRICAL CHARACTERISTICS Symbol Parameter I Input Leakage Current IL I Output Leakage Current OL V Output High Voltage Level OH V Output Low Voltage Level OL (1,2) I Operating Current CC1 I Precharge Standby Current CC2P I (In Power-Down Mode) CC2PS I Precharge Standby Current CC2N I (In Non Power-Down Mode) ...
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... IS42S32200C1 AC ELECTRICAL CHARACTERISTICS Symbol Parameter t Clock Cycle Time CK3 t CK2 t Access Time From CLK (4) AC3 t AC2 t CLK HIGH Level Width CH t CLK LOW Level Width CL t Output Data Hold Time OH t Output LOW Impedance Time LZ t Output HIGH Impedance Time HZ3 ...
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... IS42S32200C1 AC ELECTRICAL CHARACTERISTICS Symbol Parameter t Input Data To Precharge DPL3 Command Delay time t DPL2 t Input Data To Active / Refresh DAL3 Command Delay time (During Auto-Precharge) t DAL2 t Transition Time ( Write Recovery Time WR t Exit Self Refresh and Active Command XSR t Auto Refresh Period RFC ...
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... IS42S32200C1 OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER — Clock Cycle Time — Operating Frequency t READ/WRITE command to READ/WRITE command CCD t CKE to clock disable or power-down entry mode CKED t CKE to clock enable or power-down exit setup mode PED t DQM to input data delay DQD t DQM to data mask during WRITEs ...
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... IS42S32200C1 INITIALIZE AND LOAD MODE REGISTER CLK CKS CKH CKE CMH CMS CMH CMS COMMAND NOP PRECHARGE DQM0-DQM3 A0-A9 ALL BANKS A10 SINGLE BANK BA0, BA1 ALL BANKS Power-up: V Precharge CC and CLK stable all banks T = 100µs Min. 38 Tn+1 To CMH CMS ...
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... IS42S32200C1 POWER-DOWN MODE CYCLE T0 CLK t t CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM0-DQM3 A0-A9 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK DQ High-Z Two clock cycles Precharge all All banks idle, enter active banks power-down mode CAS latency = 2, 3 Integrated Silicon Solution, Inc. — www.issi.com — ...
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... IS42S32200C1 CLOCK SUSPEND MODE CLK CKS CKH CKS CKE t t CMS CMH COMMAND READ NOP t t CMS CMH DQM0-DQM3 A0-A9 (2) COLUMN A10 BA0, BA1 BANK DQ CAS latency = 2, burst length = CKH NOP NOP NOP m+1 OUT OUT Integrated Silicon Solution, Inc. — www.issi.com — ...
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... IS42S32200C1 AUTO-REFRESH CYCLE CLK t t CKS CKH CKE t t CMS CMH PRECHARGE NOP COMMAND DQM0-DQM3 A0-A9 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK ( High CAS latency = 2, 3 Integrated Silicon Solution, Inc. — www.issi.com — Rev. B 1/18/ Auto Auto NOP ...
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... IS42S32200C1 SELF-REFRESH CYCLE CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE NOP DQM0-DQM3 A0-A9 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK DQ High Precharge all Enter self active banks refresh mode CAS latency = CKS t RAS Auto Refresh CLK stable prior to exiting ...
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... IS42S32200C1 READ WITHOUT AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND t CMS DQM0-DQM3 A0-A9 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC CAS latency = 2, Burst Length = 4 CAS CAS CAS CAS Integrated Silicon Solution, Inc. — ...
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... IS42S32200C1 READ WITH AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND t CMS DQM0-DQM3 A0-A9 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC CAS latency = 2, Burst Length = 4 CAS CAS CAS CAS 44 T2 ...
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... IS42S32200C1 SINGLE READ WITHOUT AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM0-DQM3 A0-A9 ROW A10 ROW DISABLE AUTO PRECHARGE BA0, BA1 BANK DQ t RCD t RAS t RC CAS CAS CAS CAS latency = 2, Burst Length = 1 CAS Integrated Silicon Solution, Inc. — www.issi.com — ...
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... IS42S32200C1 SINGLE READ WITH AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM0-DQM3 A0-A9, ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC CAS latency = 2, Burst Length = 1 CAS CAS CAS CAS NOP NOP READ NOP ...
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... IS42S32200C1 ALTERNATING BANK READ ACCESSES CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM0-DQM3 A0-A9 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK BANK 0 RCD t RRD t - BANK 0 RAS t - BANK 0 RC Integrated Silicon Solution, Inc. — www.issi.com — ...
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... IS42S32200C1 READ - FULL-PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP READ t CMS DQM0-DQM3 A0-A9, ROW COLUMN A10 ROW BA0, BA1 BANK BANK DQ t RCD NOP NOP NOP t CMH OUT OUT each row (x32) has CAS Latency 256 locations ...
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... IS42S32200C1 READ - DQM OPERATION CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM0-DQM3 A0-A9 ROW ENABLE AUTO PRECHARGE A10 ROW DISABLE AUTO PRECHARGE BA0, BA1 BANK DQ t RCD CAS CAS Latency = 2, Burst Length = 4 CAS CAS CAS Integrated Silicon Solution, Inc. — www.issi.com — ...
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... IS42S32200C1 WRITE - WITHOUT AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM0-DQM3 A0-A9 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Burst Length = WRITE NOP NOP NOP t t CMS ...
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... IS42S32200C1 WRITE - WITH AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND t CMS DQM0-DQM3 A0-A9 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK RCD t RAS t RC Integrated Silicon Solution, Inc. — www.issi.com — Rev. B 1/18/ WRITE ...
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... IS42S32200C1 SINGLE WRITE - WITHOUT AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM0-DQM3 A0-A9 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK I/O t RCD t RAS WRITE NOP NOP PRECHARGE t t CMS CMH COLUMN m ...
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... IS42S32200C1 SINGLE WRITE - WITH AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM0-DQM3 A0-A9 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Integrated Silicon Solution, Inc. — www.issi.com — Rev. B 1/18/ NOP NOP WRITE ...
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... IS42S32200C1 ALTERNATING BANK WRITE ACCESS CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND t CMS DQM0-DQM3 A0-A9 ROW COLUMN ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK 0 BANK BANK 0 RCD t RRD t - BANK 0 RAS t - BANK WRITE NOP ACTIVE NOP t CMH ...
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... IS42S32200C1 WRITE - FULL PAGE BURST CLK t t CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0-DQM3 A0-A9 ROW A10 ROW BA0, BA1 BANK DQ t RCD Integrated Silicon Solution, Inc. — www.issi.com — Rev. B 1/18/ WRITE NOP NOP t t CMS CMH ...
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... IS42S32200C1 WRITE - DQM OPERATION CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM0-DQM3 A0-A9 ROW A10 ROW BA0, BA1 BANK DQ t RCD WRITE NOP NOP t t CMS CMH COLUMN m ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE BANK Integrated Silicon Solution, Inc. — www.issi.com — ...
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... TSOP II IS42S32200C1-7TL 400-mil TSOP II, Lead free IS42S32200C1-7B 90-ball BGA IS42S32200C1-7BL 90-ball BGA, Lead-free Order Part No. Package IS42S32200C1-6TI 400-mil TSOP II IS42S32200C1-6TLI 400-mil TSOP II, Lead free IS42S32200C1-6BI 90-ball BGA IS42S32200C1-6BLI 90-ball BGA, Lead-free IS42S32200C1-7TI 400-mil TSOP II IS42S32200C1-7TLI 400-mil TSOP II, Lead free IS42S32200C1-7BI ...
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PACKAGING INFORMATION Mini Ball Grid Array Package Code: B (90-Ball SEATING PLANE mBGA - 8mm ...
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PACKAGING INFORMATION Plastic TSOP 54–Pin, 86-Pin Package Code: T (Type II Plastic TSOP (T - Type II) Millimeters Symbol Min Max Ref. Std. No. Leads ( — 1.20 — A1 0.05 0.15 A2 ...