MT48H4M16LFB4-8:H Micron Technology Inc, MT48H4M16LFB4-8:H Datasheet - Page 32

• Manufacturer Part Number: MT48H4M16LFB4-8:H
• Description: IC SDRAM 64MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48H4M16LFB4-8:H

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 8/6ns
• Maximum Clock Rate: 125MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 50mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 28:
WRITE with Auto Precharge
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
READ with Auto Precharge Interrupted by a WRITE
Note:
3. Interrupted by a READ (with or without auto precharge): When a READ to bank m reg-
4. Interrupted by a WRITE (with or without auto precharge): When a WRITE to bank m
Internal
States
isters, it will interrupt a WRITE on bank n, with the data-out appearing 2 or 3 clocks
later, depending on CL. The precharge to bank n will begin after
t
will be data-in registered one clock prior to the READ to bank m (see Figure 29 on
page 33).
registers, it will interrupt a WRITE on bank n. The precharge to bank n will begin after
t
data WRITE to bank n will be data registered one clock prior to a WRITE to bank m
(see Figure 30 on page 33).
WR begins when the READ to bank m is registered. The last valid WRITE to bank n
WR is met, where
DQM is HIGH at T2 to prevent D
Command
Bank m
Address
Bank n
DQM
CLK
DQ
1
Active
Page
READ - AP
Bank n,
Bank n
Col a
T0
t
WR begins when the WRITE to bank m is registered. The last valid
READ with BL = 4
Page active
T1
NOP
CL = 3 (Bank n)
32
OUT
T2
NOP
a + 1 from contending with D
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
D
NOP
OUT
a
64Mb: 4 Meg x 16 Mobile SDRAM
WRITE - AP
Bank m,
Transitioning Data
Col d
Bank m
T4
D
d
IN
Interrupt burst, precharge
WRITE with BL = 4
T5
d + 1
NOP
D
IN
t
RP - Bank n
©2006 Micron Technology, Inc. All rights reserved.
IN
T6
NOP
d + 2
t
D
d at T4.
WR is met, where
IN
Don’t Care
Operations
T7
t WR - Bank m
d + 3
NOP
D
IN
W rite-Bank
Idle