EVAL-ADXL343Z-M Analog Devices, EVAL-ADXL343Z-M Datasheet - Page 13

• Manufacturer Part Number: EVAL-ADXL343Z-M
• Description: Acceleration Sensor Development Tools EB
• Manufacturer: Analog Devices

Specifications of EVAL-ADXL343Z-M

• Rohs: yes
• Tool Is For Evaluation Of: ADXL343
• Acceleration: 2 g, 4 g, 8 g, 16 g
• Sensing Axis: Triple Axis
• Interface Type: I2C, SPI
• Operating Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Current: 140 uA
• Output Type: Digital
• Product: Evaluation Systems
• Sensitivity: 256 LSB/g, 128 LSB/g, 64 LSB/g, 32 LSG/g
• Factory Pack Quantity: 1

Data Sheet
SERIAL COMMUNICATIONS
I
the
pin is tied high to V
to V
no default mode if the CS pin is left unconnected. Therefore, not
taking these precautions may result in an inability to communicate
with the part. In SPI mode, the CS pin is controlled by the bus
master. In both SPI and I
from the
during writes to the ADXL343.
SPI
For SPI, either 3- or 4-wire configuration is possible, as shown in
the connection diagrams in Figure 24 and Figure 25. Clearing the
SPI bit (Bit D6) in the DATA_FORMAT register (Address 0x31)
selects 4-wire mode, whereas setting the SPI bit selects 3-wire
mode. The maximum SPI clock speed is 5 MHz with 100 pF
maximum loading, and the timing scheme follows clock polarity
(CPOL) = 1 and clock phase (CPHA) = 1. If power is applied to
the
processor are configured, the CS pin should be brought high
before changing the clock polarity and phase. When using 3-wire
SPI, it is recommended that the SDO pin be either pulled up to
V
CS is the serial port enable line and is controlled by the SPI
master. This line must go low at the start of a transmission and
high at the end of a transmission, as shown in Figure 27. SCLK
is the serial port clock and is supplied by the SPI master. SCLK
should idle high during a period of no transmission. SDI and
SDO are the serial data input and output, respectively. Data is
updated on the falling edge of SCLK and should be sampled on
the rising edge of SCLK.
To read or write multiple bytes in a single transmission, the
multiple-byte bit, located after the R/ W bit in the first byte transfer
2
C and SPI digital communications are available. In both cases,
DD I/O
ADXL343
ADXL343
DD I/O
or pulled down to GND via a 10 kΩ resistor.
ADXL343
or be driven by an external controller because there is
operates as a slave. I
before the clock polarity and phase of the host
Figure 24. 3-Wire SPI Connection Diagram
Figure 25. 4-Wire SPI Connection Diagram
ADXL343
ADXL343
DD I/O
to the master device should be ignored
SCLK
SCLK
SDIO
SDO
SDO
SDI
CS
CS
. The CS pin should always be tied high
2
C modes of operation, data transmitted
2
C mode is enabled if the CS
PROCESSOR
PROCESSOR
CS
MOSI
MISO
SCLK
CS
MOSI
MISO
SCLK
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(MB in Figure 27 to Figure 29), must be set. After the register
addressing and the first byte of data, each subsequent set of
clock pulses (eight clock pulses) causes the
to the next register for a read or write. This shifting continues
until the clock pulses cease and CS is deasserted. To perform reads or
writes on different, nonsequential registers, CS must be deasserted
between transmissions and the new register must be addressed
separately.
The timing diagram for 3-wire SPI reads or writes is shown
in Figure 29. The 4-wire equivalents for SPI writes and reads
are shown in Figure 27 and Figure 28, respectively. For correct
operation of the part, the logic thresholds and timing parameters
in Table 9 and Table 10 must be met at all times.
Use of the 3200 Hz and 1600 Hz output data rates is only
recommended with SPI communication rates greater than or
equal to 2 MHz. The 800 Hz output data rate is recommended
only for communication speeds greater than or equal to 400 kHz,
and the remaining data rates scale proportionally. For example,
the minimum recommended communication speed for a 200 Hz
output data rate is 100 kHz. Operation at an output data rate
above the recommended maximum may result in undesirable
effects on the acceleration data, including missing samples or
additional noise.
Preventing Bus Traffic Errors
The
tions and for enabling I
a SPI bus with multiple devices, its CS pin is held high while the
master communicates with the other devices. There may be
conditions where a SPI command transmitted to another device
looks like a valid I
interprets this as an attempt to communicate in I
may interfere with other bus traffic. Unless bus traffic can be
adequately controlled to assure such a condition never occurs,
it is recommended to add a logic gate in front of the SDI pin
as shown in Figure 26. This OR gate holds the SDA line high
when CS is high to prevent SPI bus traffic at the
from appearing as an I
recommendation applies only in cases where the
is used on a SPI bus with multiple devices.
Figure 26. Recommended SPI Connection Diagram when Using Multiple SPI
ADXL343
CS pin is used both for initiating SPI transac-
ADXL343
2
C command. In this case, the
SCLK
SDIO
SDO
CS
Devices on a Single Bus
2
C start command. Note that this
2
C mode. When the
PROCESSOR
CS
MOSI
MISO
SCLK
ADXL343
ADXL343
ADXL343
ADXL343
2
ADXL343
C mode, and
ADXL343
to point
is used on