EVAL-ADXL350Z-S Analog Devices, EVAL-ADXL350Z-S Datasheet - Page 27

• Manufacturer Part Number: EVAL-ADXL350Z-S
• Description: Daughter Cards & OEM Boards EB
• Manufacturer: Analog Devices
• Series: ADXL350r

Specifications of EVAL-ADXL350Z-S

• Rohs: yes
• Product: Satellite Boards
• Description/function: 3 axis accelerometer evaluation board
• Interface Type: I2C, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2 V to 3.6 V
• Factory Pack Quantity: 1
• For Use With: ADXL350

Data Sheet
Register 0x32 to Register 0x37—DATAX0, DATAX1,
DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only)
These six bytes (Register 0x32 to Register 0x37) are eight bits
each and hold the output data for each axis. Register 0x32 and
Register 0x33 hold the output data for the x-axis, Register 0x34 and
Register 0x35 hold the output data for the y-axis, and Register 0x36
and Register 0x37 hold the output data for the z-axis. The output
data is twos complement, with DATAx0 as the least significant
byte and DATAx1 as the most significant byte, where x represent X,
Y, or Z. The DATA_FORMAT register (Address 0x31) controls
the format of the data. It is recommended that a multiple-byte
read of all registers be performed to prevent a change in data
between reads of sequential registers.
Register 0x38—FIFO_CTL (Read/Write)
D7
FIFO_MODE
FIFO_MODE Bits
These bits set the FIFO mode, as described in Table 20.
Table 20. FIFO Modes
D7
0
0
1
1
Trigger Bit
A value of 0 in the trigger bit links the trigger event of trigger mode
to INT1, and a value of 1 links the trigger event to INT2.
Setting
D6
0
1
0
1
D6
Mode
Bypass
FIFO
Stream
Trigger
D5
Trigger
Function
FIFO is bypassed.
FIFO collects up to 32 values and then
stops collecting data, collecting new data
only when FIFO is not full.
FIFO holds the last 32 data values. When
FIFO is full, the oldest data is overwritten
with newer data.
When triggered by the trigger bit, FIFO
holds the last data samples before the
trigger event and then continues to collect
data until full. New data is collected only
when FIFO is not full.
D4
D3
Samples
D2
D1
D0
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Samples Bits
The function of these bits depends on the FIFO mode selected
(see Table 21). Entering a value of 0 in the samples bits immediately
sets the watermark status bit in the INT_SOURCE register,
regardless of which FIFO mode is selected. Undesirable operation
may occur if a value of 0 is used for the samples bits when trigger
mode is used.
Table 21. Samples Bits Functions
FIFO Mode
Bypass
FIFO
Stream
Trigger
0x39—FIFO_STATUS (Read Only)
D7
FIFO_TRIG
FIFO_TRIG Bit
A 1 in the FIFO_TRIG bit corresponds to a trigger event occurring,
and a 0 means that a FIFO trigger event has not occurred.
Entries Bits
These bits report how many data values are stored in FIFO.
Access to collect the data from FIFO is provided through the
DATAX, DATAY, and DATAZ registers. FIFO reads must be
done in burst or multiple-byte mode because each FIFO level is
cleared after any read (single- or multiple-byte) of FIFO. FIFO
stores a maximum of 32 entries, which equates to a maximum
of 33 entries available at any given time because an additional
entry is available at the output filter of the device.
Samples Bits Function
None.
Specifies how many FIFO entries are needed to
trigger a watermark interrupt.
Specifies how many FIFO entries are needed to
trigger a watermark interrupt.
Specifies how many FIFO samples are retained in
the FIFO buffer before a trigger event.
D6
0
D5
D4
D3
Entries
D2
ADXL350
D1
D0