EVAL-ADXL350Z-S Analog Devices, EVAL-ADXL350Z-S Datasheet - Page 21

• Manufacturer Part Number: EVAL-ADXL350Z-S
• Description: Daughter Cards & OEM Boards EB
• Manufacturer: Analog Devices
• Series: ADXL350r

Specifications of EVAL-ADXL350Z-S

• Rohs: yes
• Product: Satellite Boards
• Description/function: 3 axis accelerometer evaluation board
• Interface Type: I2C, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2 V to 3.6 V
• Factory Pack Quantity: 1
• For Use With: ADXL350

Data Sheet
INTERRUPTS
The
INT1 and INT2. Each interrupt function is described in detail
in this section. All functions can be used simultaneously, with
the only limiting feature being that some functions may need
to share interrupt pins. Interrupts are enabled by setting the
appropriate bit in the INT_ENABLE register (Address 0x2E)
and are mapped to either the INT1 or INT2 pin based on the
contents of the INT_MAP register (Address 0x2F). It is recom-
mended that interrupt bits be configured with the interrupts
disabled, preventing interrupts from being accidentally triggered
during configuration. This can be done by writing a value of 0x00
to the INT_ENABLE register.
Clearing interrupts is performed either by reading the data
registers (Address 0x32 to Address 0x37) until the interrupt
condition is no longer valid for the data-related interrupts or by
reading the INT_SOURCE register (Address 0x30) for the
remaining interrupts. This section describes the interrupts that can
be set in the INT_ENABLE register and monitored in the
INT_SOURCE register.
DATA_READY
The DATA_READY bit is set when new data is available and is
cleared when no new data is available.
SINGLE_TAP
The SINGLE_TAP bit is set when a single acceleration event
that is greater than the value in the THRESH_TAP register
(Address 0x1D) occurs for less time than is specified in
the DUR register (Address 0x21).
DOUBLE_TAP
The DOUBLE_TAP bit is set when two acceleration events
that are greater than the value in the THRESH_TAP register
(Address 0x1D) occur for less time than is specified in the
DUR register (Address 0x21), with the second tap starting after
the time specified by the latent register (Address 0x22) but within
the time specified in the window register (Address 0x23). See
the Tap Detection section for more details.
Activity
The activity bit is set when acceleration greater than the value
stored in the THRESH_ACT register (Address 0x24) is
experienced.
Inactivity
The inactivity bit is set when acceleration of less than the value
stored in the THRESH_INACT register (Address 0x25) is experi-
enced for more time than is specified in the TIME_INACT
register (Address 0x26). The maximum value for TIME_INACT
is 255 sec.
FREE_FALL
The FREE_FALL bit is set when acceleration of less than the
value stored in the THRESH_FF register (Address 0x28) is
experienced for more time than is specified in the TIME_FF
ADXL350
provides two output pins for driving interrupts:
Rev. 0 | Page 21 of 36
register (Address 0x29). The FREE_FALL interrupt differs from
the inactivity interrupt as follows: all axes always participate, the
timer period is much smaller (1.28 sec maximum), and the mode
of operation is always dc-coupled.
Watermark
The watermark bit is set when the number of samples in FIFO
equals the value stored in the samples bits (Register FIFO_CTL,
Address 0x38). The watermark bit is cleared automatically when
FIFO is read, and the content returns to a value below the value
stored in the samples bits.
Overrun
The overrun bit is set when new data replaces unread data.
The precise operation of the overrun function depends on the
FIFO mode. In bypass mode, the overrun bit is set when new data
replaces unread data in the DATAX, DATAY, and DATAZ registers
(Address 0x32 to Address 0x37). In all other modes, the overrun
bit is set when FIFO is filled. The overrun bit is automatically
cleared when the contents of FIFO are read.
FIFO
The
embedded 32-level FIFO that can be used to minimize host
processor burden. This buffer has four modes: bypass, FIFO,
stream, and trigger (see Table 20). Each mode is selected by
the settings of the FIFO_MODE bits in the FIFO_CTL register
(Address 0x38).
Bypass Mode
In bypass mode, FIFO is not operational and, therefore,
remains empty.
FIFO Mode
In FIFO mode, data from measurements of the x-, y-, and z-
axes are stored in FIFO. When the number of samples in FIFO
equals the level specified in the samples bits of the FIFO_CTL
register (Address 0x38), the watermark interrupt is set. FIFO
continues accumulating samples until it is full (32 samples from
measurements of the x-, y-, and z-axes) and then stops collecting
data. After FIFO stops collecting data, the device continues to
operate; therefore, features such as tap detection can be used
after FIFO is full. The watermark interrupt continues to occur
until the number of samples in FIFO is less than the value
stored in the samples bits of the FIFO_CTL register.
Stream Mode
In stream mode, data from measurements of the x-, y-, and
z-axes are stored in FIFO. When the number of samples in FIFO
equals the level specified in the samples bits of the FIFO_CTL
register (Address 0x38), the watermark interrupt is set. FIFO
continues accumulating samples and holds the latest 32 samples
from measurements of the x-, y-, and z-axes, discarding older
data as new data arrives. The watermark interrupt continues
occurring until the number of samples in FIFO is less than the
value stored in the samples bits of the FIFO_CTL register.
ADXL350
contains patent pending technology for an
ADXL350