EVAL-ADXL350Z-S Analog Devices, EVAL-ADXL350Z-S Datasheet - Page 26

• Manufacturer Part Number: EVAL-ADXL350Z-S
• Description: Daughter Cards & OEM Boards EB
• Manufacturer: Analog Devices
• Series: ADXL350r

Specifications of EVAL-ADXL350Z-S

• Rohs: yes
• Product: Satellite Boards
• Description/function: 3 axis accelerometer evaluation board
• Interface Type: I2C, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2 V to 3.6 V
• Factory Pack Quantity: 1
• For Use With: ADXL350

ADXL350
to FIFO, and switches the sampling rate to one specified by the
wakeup bits. In sleep mode, only the activity function can be used.
When clearing the sleep bit, it is recommended that the part be
placed into standby mode and then set back to measurement
mode with a subsequent write. This is done to ensure that the
device is properly biased if sleep mode is manually disabled;
otherwise, the first few samples of data after the sleep bit is
cleared may have additional noise, especially if the device was
asleep when the bit was cleared.
Wakeup Bits
These bits control the frequency of readings in sleep mode as
described in Table 18.
Table 18. Frequency of Readings in Sleep Mode
D1
0
0
1
1
Register 0x2E—INT_ENABLE (Read/Write)
D7
DATA_READY
D3
Inactivity
Setting bits in this register to a value of 1 enables their respective
functions to generate interrupts, whereas a value of 0 prevents
the functions from generating interrupts. The DATA_READY,
watermark, and overrun bits enable only the interrupt output;
the functions are always enabled. It is recommended that interrupts
be configured before enabling their outputs.
Register 0x2F—INT_MAP (Read/Write)
D7
DATA_READY
D3
Inactivity
Any bits set to 0 in this register send their respective interrupts to
the INT1 pin, whereas bits set to 1 send their respective interrupts
to the INT2 pin. All selected interrupts for a given pin are OR’ e d.
Register 0x30—INT_SOURCE (Read Only)
D7
DATA_READY
D3
Inactivity
Setting
D0
0
1
0
1
D6
SINGLE_TAP
D2
FREE_FALL
D6
SINGLE_TAP
D2
FREE_FALL
D6
SINGLE_TAP
D2
FREE_FALL
Frequency (Hz)
8
4
2
1
D5
DOUBLE_TAP
D1
Watermark
D5
DOUBLE_TAP
D1
Watermark
D5
DOUBLE_TAP
D1
Watermark
D4
Activity
D0
Overrun
D4
Activity
D0
Overrun
D4
Activity
D0
Overrun
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Bits set to 1 in this register indicate that their respective functions
have triggered an event, whereas a value of 0 indicates that the
corresponding event has not occurred. The DATA_READY,
watermark, and overrun bits are always set if the corresponding
events occur, regardless of the INT_ENABLE register settings,
and are cleared by reading data from the DATAX, DATAY, and
DATAZ registers. The DATA_READY and watermark bits may
require multiple reads, as indicated in the FIFO mode descriptions
in the FIFO section. Other bits, and the corresponding interrupts,
are cleared by reading the INT_SOURCE register.
Register 0x31—DATA_FORMAT (Read/Write)
D7
SELF_TEST
The DATA_FORMAT register controls the presentation of data
to Register 0x32 through Register 0x37. All data, except that for
the ±8 g range, is clipped internally to avoid rollover.
SELF_TEST Bit
A setting of 1 in the SELF_TEST bit applies a self-test force to
the sensor, causing a shift in the output data. A value of 0 disables
the self-test force.
SPI Bit
A value of 1 in the SPI bit sets the device to 3-wire SPI mode,
and a value of 0 sets the device to 4-wire SPI mode.
INT_INVERT Bit
A value of 0 in the INT_INVERT bit sets the interrupts to active
high, and a value of 1 sets the interrupts to active low.
FULL_RES Bit
When this bit is set to a value of 1, the device is in full resolution
mode, where the output resolution increases with the g range
set by the range bits to maintain a 2 mg/LSB scale factor. When
the FULL_RES bit is set to 0, the device is in 10-bit mode, and
the range bits determine the maximum g range and scale factor.
Justify Bit
A setting of 1 in the Justify bit selects left (MSB) justified mode,
and a setting of 0 selects right justified mode with sign extension.
Range Bits
These bits set the g range as described in Table 19.
Table 19. g Range Setting
D1
0
0
1
1
Setting
D0
0
1
0
1
D6
SPI
D5
INT_INVERT
g Range
±1 g
±2 g
±4 g
±8 g
D4
0
D3
FULL_RES
Data Sheet
D2
Justify
D1
Range
D0