EVAL-ADXL350Z-S Analog Devices, EVAL-ADXL350Z-S Datasheet - Page 16

• Manufacturer Part Number: EVAL-ADXL350Z-S
• Description: Daughter Cards & OEM Boards EB
• Manufacturer: Analog Devices
• Series: ADXL350r

Specifications of EVAL-ADXL350Z-S

• Rohs: yes
• Product: Satellite Boards
• Description/function: 3 axis accelerometer evaluation board
• Interface Type: I2C, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2 V to 3.6 V
• Factory Pack Quantity: 1
• For Use With: ADXL350

ADXL350
SERIAL COMMUNICATIONS
I
the
the CS pin is tied high to V
tied high to V
because there is no default mode if the CS pin is left
unconnected. Not taking this precaution may result in an inability
to communicate with the part. In SPI mode, the CS pin is
controlled by the bus master.
In both SPI and I
ADXL350
the ADXL350.
SPI
For SPI, either 3- or 4-wire configuration is possible, as shown
in the connection diagrams in Figure 49 and Figure 50. Clearing
the SPI bit in the DATA_FORMAT register (Address 0x31) selects
4-wire mode, whereas setting the SPI bit selects 3-wire mode.
The maximum SPI clock speed is 5 MHz with 100 pF maximum
loading, and the timing scheme follows clock polarity (CPOL) = 1
and clock phase (CPHA) = 1.
CS is the serial port enable line and is controlled by the SPI master.
This line must go low at the start of a transmission and high at
the end of a transmission, as shown in Figure 52. SCLK is the
serial port clock and is supplied by the SPI master. It is stopped
high when CS is high during a period of no transmission. SDI
and SDO are the serial data input and output, respectively. Data
should be sampled at the rising edge of SCLK.
2
C and SPI digital communications are possible and regardless,
ADXL350
to the master device should be ignored during writes to
always operates as a slave. I
DD I/O
Figure 49. 3-Wire SPI Connection Diagram
Figure 50. 4-Wire SPI Connection Diagram
ADXL350
ADXL350
ADXL350
ADXL350
2
C modes of operation, data transmitted from the
or be driven by an external controller
SCLK
SCLK
SDIO
SDO
SDO
SDI
CS
CS
DD I/O
. The CS pin should always be
PROCESSOR
PROCESSOR
D OUT
D IN/OUT
D OUT
D OUT
D OUT
D IN
D OUT
2
C mode is enabled if
Rev. 0 | Page 16 of 36
To read or write multiple bytes in a single transmission, the
multiple-byte bit, located after the R/ W bit in the first byte
transfer (MB in Figure 52 to Figure 54), must be set. After the
register addressing and the first byte of data, each subsequent
set of clock pulses (eight clock pulses) causes the
point to the next register for a read or write. This shifting continues
until the clock pulses cease and CS is deasserted. To perform
reads or writes on different, nonsequential registers, CS must
be deasserted between transmissions and the new register must
be addressed separately. The timing diagram for 3-wire SPI
reads or writes is shown in Figure 54. The 4-wire equivalents
for SPI writes and reads are shown in Figure 52 and Figure 53,
respectively.
Preventing Bus Traffic Errors
The
tions, and for enabling I
on an SPI bus with multiple devices, its CS pin is held high
while the master communicates with the other devices. There
may be conditions where an SPI command transmitted to
another device looks like a valid I
ADXL350
I
traffic can be adequately controlled to assure such a condition
never occurs, it is recommended to add a logic gate in front of
the SDI pin as shown in Figure 51. This OR gate will hold the
SDA line high when CS is high to prevent SPI bus traffic at the
ADXL350
Figure 51. Recommended SPI Connection Diagram when Using Multiple SPI
2
C mode, and could interfere with other bus traffic. Unless bus
ADXL350
would interpret this as an attempt to communicate in
from appearing as an I
CS pin is used both for initiating SPI transact-
ADXL350
ADXL350
SCLK
SDIO
SDO
CS
Devices on a Single Bus
2
C mode. When the
2
2
C start command.
C command. In this case, the
PROCESSOR
D OUT
D IN/OUT
D OUT
ADXL350
Data Sheet
ADXL350
is used
to