MAX5825PMB1# Maxim Integrated, MAX5825PMB1# Datasheet - Page 27

• Manufacturer Part Number: MAX5825PMB1#
• Description: Data Conversion IC Development Tools MAX5825 Peripheral Module
• Manufacturer: Maxim Integrated
• Type: DACr
• Series: MAX5823, MAX5824, MAX5825r

Specifications of MAX5825PMB1#

• Rohs: yes
• Product: Peripheral Module
• Tool Is For Evaluation Of: MAX5825
• Interface Type: I2C
• Operating Supply Voltage: 2.048 V, 2.5 V, 4.096 V
• Description/function: Peripheral module provides the necessary hardware to interface the MAX5825 8-channel DAC to any system that utilizes Pmod-compatible expansion ports configurable for IýC communication
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Part # Aliases: 90-58250#PM1
• For Use With: MAX5285 8-Channel DAC

The REF command (B[23:20] = 0010) updates the global
reference setting used for all DAC channels. If an internal
reference mode is selected, bit RF2 (B18) defines the
reference power mode. If RF2 is set to zero (default), the
reference will be powered down any time all DAC chan-
nels are powered down (i.e. the device is in STANDBY
mode). If RF2 is set to one, the reference will remain pow-
ered even if all DAC channels are powered down, allow-
ing continued operation of external circuitry (note in this
mode the low current shutdown state is not available).
This command is inaccessible when a watchdog timeout
has occurred and the watchdog timer is configured with
a safety level of high or max.
The SW_GATE_CLR command (B[23:0] = 0011_0000_
1001_0110_0011_0000) will remove any existing GATE
condition initiated by a previous SW_GATE_SET comand.
The SW_GATE_SET command (B[23:0] = 0011_0001_
1001_0110_0011_0000) will initiate a GATE condition.
Any DACs configured with GTB = 0 (see the
Command
selected DEFAULT value until the GATE condition is later
removed by a subsequent SW_GATE_CLR command.
While in gate mode, the CODE and DAC registers con-
Table 8. REF Command Format
Maxim Integrated
Output DACs with Internal Reference and I
B23 B22 B21 B20 B19
0
REF Command
Default Value →
0
1
section) will have their outputs held at the
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Command Byte
0
0
B18
RF2
0
SW_GATE_CLR Command
SW_GATE_SET Command
RF1 RF0
B17
REF Mode:
01: 2.5V
10: 2.0V
11: 4.0V
0
00: EXT
B16 B15 B14 B13 B12 B11 B10 B9
0
REF Command
X
X
CONFIG
MAX5823/MAX5824/MAX5825
X
X
X
X
Data High Byte
Don’t Care
X
X
tinue to function normally and are not reset (unless reset
by a watchdog timeout).
The WD_REFRESH command (B[23:0] = 0011_0010_
1001_0110_0011_0000) will refresh the watchdog timer.
This is the only command which will refresh the watch-
dog timer if the device is configured with a safety level of
medium, high, or max. Use this command to prevent the
watchdog timer from timing out.
A WD_RESET command (B[23:0] = 0011_0011_
1001_0110_0011_0000) will reset the watchdog interrupt
(timeout) status and refresh the watchdog timer. Use this
command to reset the IRQ timeout condition after the
watchdog timer has timed out. Any DACs impacted by an
existing timeout condition will return to normal operation.
A software clear command (B[23:0] = 0011_0100_
001_0110_0011_0000) will clear the contents of the CODE
and DAC registers to the DEFAULT state for all channels
configured with CLB = 0 (see CONFIG command).
A software reset command (B[23:0] = 0011_0101_
1001_0110_0011_0000) will reset all CODE, DAC,
and configuration registers to their defaults (including
POWER, DEFAULT, CONFIG, WDOG, and REF regis-
ters), simulating a power-on reset.
X
X
X
X
X
X
B8 B7 B6 B5 B4 B3 B2 B1 B0
X
X
X
X
X
X
WD_REFRESH Command
2
SW_CLEAR Command
C Interface
WD_RESET Command
SW_RESET Command
X
X
Data Low Byte
Don’t Care
X
X
X
X
X
X
X
X
X
X
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