MAX5825PMB1# Maxim Integrated, MAX5825PMB1# Datasheet - Page 16

• Manufacturer Part Number: MAX5825PMB1#
• Description: Data Conversion IC Development Tools MAX5825 Peripheral Module
• Manufacturer: Maxim Integrated
• Type: DACr
• Series: MAX5823, MAX5824, MAX5825r

Specifications of MAX5825PMB1#

• Rohs: yes
• Product: Peripheral Module
• Tool Is For Evaluation Of: MAX5825
• Interface Type: I2C
• Operating Supply Voltage: 2.048 V, 2.5 V, 4.096 V
• Description/function: Peripheral module provides the necessary hardware to interface the MAX5825 8-channel DAC to any system that utilizes Pmod-compatible expansion ports configurable for IýC communication
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Part # Aliases: 90-58250#PM1
• For Use With: MAX5285 8-Channel DAC

The external reference input has a typical input impedance
of 100kI and accepts an input voltage from +1.24V to V
Apply an external voltage between REF and GND to use
an external reference. The MAX5823/MAX5824/MAX5825
power up and reset to external reference mode. Visit
www.maximintegrated.com/products/references
list of available external voltage-reference devices.
The MAX5823/MAX5824/MAX5825 feature a pin select-
able DAC reset state using the M/Z input. Upon a power-
on reset, all CODE and DAC data registers are reset to
zero scale (M/Z = GND) or midscale (M/Z = V
referenced to V
valid at the time the device is powered up—connect M/Z
directly to V
The MAX5823/MAX5824/MAX5825 feature an active-low
asynchronous LDAC logic input that allows DAC outputs
to update simultaneously. Connect LDAC to V
keep LDAC high during normal operation when the
device is controlled only through the serial interface.
Drive LDAC low to update the DAC outputs with data
from the CODE registers. Holding LDAC low causes the
DAC registers to become transparent and CODE data is
passed through to the DAC registers immediately updat-
ing the DAC outputs. A software CONFIG command can
be used to configure the LDAC operation of each DAC
independently.
The MAX5823/MAX5824/MAX5825 feature an asynchro-
nous active-low CLR logic input that simultaneously
sets all selected DAC outputs to their programmable
DEFAULT states. Driving CLR low clears the contents of
both the CODE and DAC registers and also ignores any
on-going I
ated with a DAC configured to accept clear operations.
To allow a new I
ing the t
command can be used to configure the clear operation of
each DAC independently.
The MAX5823/MAX5824/MAX5825 feature an interface
watchdog timer with programmable timeout duration. This
monitors the I/O interface for activity and integrity. If the
Maxim Integrated
Output DACs with Internal Reference and I
CLRSTA
2
C command which modifies registers associ-
DD
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
DD
or GND.
timing requirement. A software CONFIG
2
C command, drive CLR high, satisfy-
(not V
DDIO
Load DAC (LDAC) Input
). In addition, M/Z must be
External Reference
Watchdog Feature
Clear (CLR) Input
M/Z Input
DD
). M/Z is
DDIO
MAX5823/MAX5824/MAX5825
for a
DD
or
.
Figure 2. I
watchdog is enabled, the host processor must write a valid
command to the device within the timeout period to prevent
a timeout. If the watchdog is allowed to timeout, selected
DAC outputs are returned to the programmable DEFAULT
state, protecting the system against control faults.
By default, all watchdog features are disabled; users
wishing to activate any watchdog feature must configure
the device accordingly. Individual DAC channels can
be configured using the CONFIG command to accept
the watchdog alarm and to gate, clear, or hold their out-
puts in response to an alarm. A watchdog refresh event
and watchdog behavior upon timeout is defined by a
programmable safety level using the WDOG_CONFIG
command.
The MAX5823/MAX5824/MAX5825 feature an active-low
open-drain interrupt output indicating to the host when a
watchdog timeout has occurred.
SCL
SDA
INVALID START/STOP PULSE PAIRINGS-ALL WILL BE RECOGNIZED AS STARTS
2
P
C START, Repeated START, and STOP Conditions
S
VALID START, REPEATED START, AND STOP PULSES
S
S
P
Sr
2
C Interface
P
S
IRQ Output
P
P
16