MAX5825PMB1# Maxim Integrated, MAX5825PMB1# Datasheet - Page 18

• Manufacturer Part Number: MAX5825PMB1#
• Description: Data Conversion IC Development Tools MAX5825 Peripheral Module
• Manufacturer: Maxim Integrated
• Type: DACr
• Series: MAX5823, MAX5824, MAX5825r

Specifications of MAX5825PMB1#

• Rohs: yes
• Product: Peripheral Module
• Tool Is For Evaluation Of: MAX5825
• Interface Type: I2C
• Operating Supply Voltage: 2.048 V, 2.5 V, 4.096 V
• Description/function: Peripheral module provides the necessary hardware to interface the MAX5825 8-channel DAC to any system that utilizes Pmod-compatible expansion ports configurable for IýC communication
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Part # Aliases: 90-58250#PM1
• For Use With: MAX5285 8-Channel DAC

The slave address is defined as the seven most sig-
nificant bits (MSBs) followed by the R/W bit. See
Figure
4 LSBs determined by ADDR1 and ADDR0 as shown in
Table
MAX5824/MAX5825 for read mode. Setting the R/W bit to
0 configures the MAX5823/MAX5824/MAX5825 for write
mode. The slave address is the first byte of informa-
tion sent to the MAX5823/MAX5824/MAX5825 after the
START condition.
The MAX5823/MAX5824/MAX5825 has the ability to
detect an unconnected (N.C.) state on the ADDR_ inputs
for additional address flexibility; if disconnecting the
ADDR_ inputs, be certain to minimize all loading on the
ADDR_ inputs (i.e. provide a landing for ADDR_, but do
not allow any board traces).
A broadcast address is provided for the purpose of
updating or configuring all MAX5823/MAX5824/MAX5825
devices on a given I
Figure 3. I
Figure 4. I
Maxim Integrated
Output DACs with Internal Reference and I
SDA
SCL
CONDITION
START
SDA
SCL
1. Setting the R/W bit to 1 configures the MAX5823/
4. The three most significant bits are 001 with the
2
2
C Acknowledge
C Single Register Write Sequence
START
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
1
BYTE #1: I
0
WRITE ADDRESS
0
2
2
2
C SLAVE ADDRESS
1
C bus. All MAX5823/MAX5824/
A3 A2 A1 A0 W
I
A
2
C Broadcast Address
NOT ACKNOWLEDGE
ACK. GENERATED BY MAX5823/MAX5824/MAX5825
ACKNOWLEDGE
I
2
C Slave Address
A
ACKNOWLEDGMENT
23
CLOCK PULSE
BYTE #2: COMMAND BYTE
22
WRITE COMMAND
FOR
21
(B[23:16])
9
20 19 18 17
MAX5823/MAX5824/MAX5825
16
A
15 14 13 12 11 10 9
BYTE #3: DATA HIGH BYTE
MAX5825 devices acknowledge and respond to the
broadcast device address 00101000, regardless of the
state of the address pins. The broadcast mode is intend-
ed for use in write mode only (as indicated by R/W = 0 in
the address given).
In write mode, the acknowledge bit (ACK) is a clocked 9th
bit that the MAX5823/MAX5824/MAX5825 use to hand-
shake receipt of each byte of data as shown in
The MAX5823/MAX5824/MAX5825 pull down SDA during
the entire master-generated 9th clock pulse if the previous
byte is successfully received. Monitoring ACK allows for
detection of unsuccessful data transfers. An unsuccessful
data transfer occurs if a receiving device is busy or if a
system fault has occurred. In the event of an unsuccess-
ful data transfer, the bus master will retry communication.
In read mode, the master pulls down SDA during the
9th clock cycle to acknowledge receipt of data from the
MAX5823/MAX5824/MAX5825. An acknowledge is sent
by the master after each read byte to allow data transfer
to continue. A not-acknowledge is sent when the master
reads the final byte of data from the MAX5823/MAX5824/
MAX5825, followed by a STOP condition.
A command byte follows the slave address. A command
byte is typically followed by two data bytes unless it is
the last byte in the transmission. If data bytes follow the
command byte, the command byte indicates the address
of the register that is to receive the following two data
bytes. The data bytes are stored in a temporary register
and then transferred to the appropriate register during
the ACK periods between bytes. This avoids any glitch-
ing or digital feedthrough to the DACs while the interface
is active.
WRITE DATA
(B[15:8])
I
2
8
C Command Byte and Data Bytes
A
7 6 5 4 3 2 1
BYTE #4: DATA LOW BYTE
WRITE DATA
(B[7:0])
2
C Interface
0
I
2
A
C Acknowledge
COMMAND EXECUTED
STOP
Figure
18
3.