MAX5825PMB1# Maxim Integrated, MAX5825PMB1# Datasheet - Page 15

• Manufacturer Part Number: MAX5825PMB1#
• Description: Data Conversion IC Development Tools MAX5825 Peripheral Module
• Manufacturer: Maxim Integrated
• Type: DACr
• Series: MAX5823, MAX5824, MAX5825r

Specifications of MAX5825PMB1#

• Rohs: yes
• Product: Peripheral Module
• Tool Is For Evaluation Of: MAX5825
• Interface Type: I2C
• Operating Supply Voltage: 2.048 V, 2.5 V, 4.096 V
• Description/function: Peripheral module provides the necessary hardware to interface the MAX5825 8-channel DAC to any system that utilizes Pmod-compatible expansion ports configurable for IýC communication
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Part # Aliases: 90-58250#PM1
• For Use With: MAX5285 8-Channel DAC

The MAX5823/MAX5824/MAX5825 are 8-channel, low-
power, 8-/10-/12-bit buffered voltage-output DACs. The
2.7V to 5.5V wide supply voltage range and low-power
consumption accommodates most low-power and low-
voltage applications. The devices present a 100kI load
to the external reference. The internal output buffers
allow rail-to-rail operation. An internal voltage reference
is available with software selectable options of 2.048V,
2.500V, or 4.096V. The devices feature a fast 400kHz I
compatible interface. The MAX5823/MAX5824/MAX5825
include a serial-in/parallel-out shift register, internal
CODE and DAC registers, a power-on-reset (POR) circuit
to initialize the DAC outputs to zero scale (M/Z = 0) or
midscale (M/Z = 1), and control logic.
CLR is available to asynchronously clear the DAC out-
puts to a user-programmable default value, independent
of the serial interface. LDAC is available to simultane-
ously update selected DACs on one or more devices.
The MAX5823/MAX5824/MAX5825 also feature user-
configurable interface watchdog, with status indicated
by the IRQ output.
The MAX5823/MAX5824/MAX5825 include internal buf-
fers on all DAC outputs, which provide improved load
regulation for the DAC outputs. The output buffers slew
at 1V/Fs (typ) and drive as low as 2kI in parallel with
500pF. The analog supply voltage (V
maximum output voltage range of the devices since it
powers the output buffers. Under no-load conditions, the
output buffers drive from GND to V
and gain errors. With a 2kω load to GND, the output buf-
fers drive from GND to within 200mV of V
load to V
200mV of GND.
The DAC ideal output voltage is defined by:
where D = code loaded into the DAC register, V
reference voltage, N = resolution.
Maxim Integrated
Output DACs with Internal Reference and I
DD
, the output buffers drive from V
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
V
OUT
=
Detailed Description
V
REF
DAC Outputs (OUT_)
×
2
D
N
DD
DD
, subject to offset
) determines the
DD
. With a 2kω
DD
to within
MAX5823/MAX5824/MAX5825
REF
2
C-
=
The user interface is separated from the DAC logic to
minimize digital feedthrough. Within the serial interface
is an input shift register, the contents of which can be
routed to control registers, individual, or multiple DACs
as determined by the user command.
Within each DAC channel there is a CODE register
followed by a DAC latch register (see the
Functional
hold pending DAC output settings which can later be
loaded into the DAC registers. The CODE register can be
updated using both CODE and CODE_LOAD user com-
mands. The contents of the DAC register hold the current
DAC output settings. The DAC register can be updated
directly from the serial interface using the CODE_LOAD
commands or can upload the current contents of the
CODE register using LOAD commands or the LDAC
logic input.
The contents of both CODE and DAC registers are main-
tained during power-down states, so that when the DACs
are powered on, they return to their previously stored
output settings. Any CODE or LOAD commands issued
during power-down states continue to update the register
contents.
Once the device is powered up, each DAC channel can
be independently programmed with a desired RETURN
value using the RETURN command. This becomes the
value the CODE and DAC registers will use in the event
of any watchdog, clear or gate activity, as selected by
the DEFAULT command.
Hardware CLR operations and SW_CLEAR commands
return the contents of all CODE and DAC registers to their
user-selected defaults. SW_RESET commands will reset
CODE and DAC register contents to their M/Z selected
initial codes. A SW_GATE state can be used to momen-
tarily hold selected DAC outputs in their DEFAULT posi-
tions. The contents of CODE and DAC registers can
be manipulated by watchdog timer activity, enabling a
variety of safety features.
The MAX5823/MAX5824/MAX5825 include an internal
precision voltage reference that is software selectable to
be 2.048V, 2.500V, or 4.096V. When an internal reference
is selected, that voltage is available on the REF output
for other external circuitry (see the
Circuits) and can drive loads down to 25kI.
Diagram). The contents of the CODE register
Internal Register Structure
2
Internal Reference
C Interface
Typical Operating
Detailed
15