AT25DF161-MH-Y Atmel, AT25DF161-MH-Y Datasheet - Page 22

IC FLASH 16MBIT 100MHZ 8UDFN

AT25DF161-MH-Y

Manufacturer Part Number
AT25DF161-MH-Y
Description
IC FLASH 16MBIT 100MHZ 8UDFN
Manufacturer
Atmel
Datasheet

Specifications of AT25DF161-MH-Y

Format - Memory
FLASH
Memory Type
DataFLASH
Memory Size
16M (2M x 8)
Speed
100MHz
Interface
SPI, RapidS
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-UDFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT25DF161-MH-Y
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
22
Table 9-2.
Essentially, if the SPRL bit of the Status Register is in the logical “0” state (Sector Protection Registers are not locked),
then writing a 00h to the first byte of the Status Register will perform a Global Unprotect without changing the state of the
SPRL bit. Similarly, writing a 7Fh to the first byte of the Status Register will perform a Global Protect and keep the SPRL bit
in the logical “0” state. The SPRL bit can, of course, be changed to a logical “1” by writing an FFh if software-locking or
hardware-locking is desired along with the Global Protect.
If the desire is to only change the SPRL bit without performing a Global Protect or Global Unprotect, then the system can
simply write a 0Fh to the first byte of the Status Register to change the SPRL bit from a logical “1” to a logical “0”
provided the WP pin is deasserted. Likewise, the system can write an F0h to change the SPRL bit from a logical “0” to a
Atmel AT25DF161
State
WP
0
0
1
1
Current
SPRL
Value
Valid SPRL and Global Protect/Unprotect Conditions
0
1
0
1
New Write Status
Register Byte 1
7 6 5 4 3 2 1 0
0 x 0 0 0 0 x x
0 x 0 0 0 1 x x
0 x 1 1 1 0 x x
0 x 1 1 1 1 x x
1 x 0 0 0 0 x x
1 x 0 0 0 1 x x
1 x 1 1 1 0 x x
1 x 1 1 1 1 x x
0 x 0 0 0 0 x x
0 x 0 0 0 1 x x
0 x 1 1 1 0 x x
0 x 1 1 1 1 x x
1 x 0 0 0 0 x x
1 x 0 0 0 1 x x
1 x 1 1 1 0 x x
1 x 1 1 1 1 x x
0 x 0 0 0 0 x x
0 x 0 0 0 1 x x
0 x 1 1 1 0 x x
0 x 1 1 1 1 x x
1 x 0 0 0 0 x x
1 x 0 0 0 1 x x
1 x 1 1 1 0 x x
1 x 1 1 1 1 x x
x x x x x x x x
Data
Bit
Protection Operation
Global Unprotect – all Sector Protection Registers reset to 0
No change to current protection.
No change to current protection.
No change to current protection.
Global Protect – all Sector Protection Registers set to 1
Global Unprotect – all Sector Protection Registers reset to 0
No change to current protection.
No change to current protection.
No change to current protection.
Global Protect – all Sector Protection Registers set to 1
No change to the current protection level. All sectors currently protected will remain protected and
all sectors currently unprotected will remain unprotected.
The Sector Protection Registers are hard-locked and cannot be changed when the WP pin is LOW
and the current state of SPRL is 1. Therefore, a Global Protect/Unprotect will not occur. In addition,
the SPRL bit cannot be changed (the WP pin must be HIGH in order to change SPRL back to a 0).
Global Unprotect – all Sector Protection Registers reset to 0
No change to current protection.
No change to current protection.
No change to current protection.
Global Protect – all Sector Protection Registers set to 1
Global Unprotect – all Sector Protection Registers reset to 0
No change to current protection.
No change to current protection.
No change to current protection.
Global Protect – all Sector Protection Registers set to 1
No change to the current protection level. All sectors currently protected will remain
protected, and all sectors currently unprotected will remain unprotected.
The Sector Protection Registers are soft-locked and cannot be changed when the current
state of SPRL is 1. Therefore, a Global Protect/Unprotect will not occur. However, the
SPRL bit can be changed back to a 0 from a 1 since the WP pin is HIGH. To perform a
Global Protect/Unprotect, the Write Status Register command must be issued again after
the SPRL bit has been changed from a 1 to a 0.
3687E–DFLASH–11/10
SPRL
Value
New
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1

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