AT25DF161-SSH-T Atmel, AT25DF161-SSH-T Datasheet
AT25DF161-SSH-T
Specifications of AT25DF161-SSH-T
Available stocks
Related parts for AT25DF161-SSH-T
AT25DF161-SSH-T Summary of contents
Page 1
... Complies with Full Industrial Temperature Range • Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options – 8-lead SOIC (150-mil and 208-mil wide) – 8-pad Ultra Thin DFN ( 0.6mm) 16-Megabit 2.3V or 2.7V Minimum SPI Serial Flash Memory Atmel AT25DF161 Atmel RapidS 3687E–DFLASH–11/10 ...
Page 2
... EEPROM devices. The physical sectoring and the erase block sizes of the AT25DF161 have been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently ...
Page 3
... GROUND: The ground reference for the power supply. GND should be connected to the system GND ground. 3687E–DFLASH–11/10 for more details on protection features and the WP pin is used to supply the source voltage to the device. CC voltages may produce spurious results and should not be attempted. Atmel AT25DF161 Asserted whenever CC “Hold” on page 39 for additional whenever CC ...
Page 4
... Architecture Diagram illustrates the breakdown of each erase level as well as the breakdown of each physical sector. Atmel AT25DF161 4 8-UDFN (SOI HOLD SCK GND (SIO) Top View CONTROL AND PROTECTION LOGIC Y-DECODER X-DECODER I/O BUFFERS AND LATCHES SRAM DATA BUFFER Y-GATING FLASH MEMORY ARRAY ® AT25DF161 can be erased in four levels of granularity 3687E–DFLASH–11/10 ...
Page 5
... Figure 4-1. Memory Architecture Diagram 3687E–DFLASH–11/10 Atmel AT25DF161 5 ...
Page 6
... The SPI protocol defines a total of four modes of operation (mode with each mode differing in respect to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25DF161 supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any data) ...
Page 7
... Up to 100MHz 01h 0000 0001 Up to 100MHz 31h 0011 0001 Up to 100MHz F0h 1111 0000 Up to 100MHz 9Fh 1001 1111 Up to 85MHz B9h 1011 1001 Up to 100MHz ABh 1010 1011 Up to 100MHz Atmel AT25DF161 Address Dummy Data Bytes Bytes Bytes ...
Page 8
... Figure 7-1. Read Array – 1Bh Opcode CS SCK SI SO Atmel AT25DF161 8 , and the 03h opcode can be used for lower frequency read operations up CLK . The 1Bh opcode allows the highest read performance possible and can be used at any RDLF ; however, use of the 1Bh opcode at clock frequencies above f MAX ® ...
Page 9
... When the last byte (1FFFFFh) of the memory array has been read, the device will continue reading back at the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array. 3687E–DFLASH–11/10 Atmel AT25DF161 . To RDDO 9 ...
Page 10
... In addition, if the address specified by A23-A0 points to a memory location within a sector that is in the protected state (see locked down (see “Sector Lockdown” on page Atmel AT25DF161 10 “Write Enable” on page only programming a single byte ...
Page 11
... Register to a logical “1” state. To perform a Dual-Input Byte/Page Program command, an opcode of A2h must be clocked 3687E–DFLASH–11/10 “Write Enable” on page 18) to set the Write Enable Latch (WEL) bit of the Status Atmel AT25DF161 or t time to determine if the BP PP ...
Page 12
... Register will be reset back to the logical “0” state. The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly programming error arises, it will be indicated by the EPE bit in the Status Register. Atmel AT25DF161 only programming a single byte. ...
Page 13
... CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and no erase operation will be performed. 3687E–DFLASH–11/10 . BLKE Atmel AT25DF161 13 ...
Page 14
... CS pin is deasserted on uneven byte boundaries sector is in the protected or locked down state. While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device is busy. For faster throughput recommended that the Status Register be polled rather than waiting the t Atmel AT25DF161 14 time to BLKE ...
Page 15
... A program operation is not allowed to a sector that has been erase suspended program operation is attempted to an erase suspended sector, then the program operation will abort and the WEL bit in the Status Register will be reset back to 3687E–DFLASH–11/10 Table 8-1 outlines the operations that are allowed and not allowed Atmel AT25DF161 15 ...
Page 16
... Read Sector Lockdown Registers Program OTP Security Register Read OTP Security Register Status Register Commands Read Status Register Write Status Register (All Opcodes) Atmel AT25DF161 16 35) is performed while a sector is erase suspended, the suspend operation will Operation During Program Suspend Allowed Not Allowed ...
Page 17
... Operation During Program Suspend Allowed Allowed Not Allowed Not Allowed time before issuing the Program/Erase Suspend command must check the RES Atmel AT25DF161 Operation During Erase Suspend Allowed Allowed Not Allowed Not Allowed . RES 17 ...
Page 18
... CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not change. Figure 9-1. Write Enable CS SCK SI SO Atmel AT25DF161 18 3687E–DFLASH–11/10 ...
Page 19
... Sector Protection Register corresponding to the physical sector addressed by A23-A0 will be set to the logical “1” state, and the sector itself will then be protected from program and erase operations. In addition, the WEL bit in the Status Register will be reset back to the logical “0” state. 3687E–DFLASH–11/10 Atmel AT25DF161 19 ...
Page 20
... Status Register description for more details). If the Sector Protection Registers are locked, then any attempts to issue the Unprotect Sector command will be ignored, and the device will reset the WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been deasserted. Atmel AT25DF161 20 Table 9-1 for Sector Protection Register values). Every physical sector of the device 3687E– ...
Page 21
... Flash memory array will not change, and WEL bit in the Status Register will be reset back to a logical “0”. 3687E–DFLASH–11/10 “Write Status Register Byte 1” on page 33 Table 9-2 details the conditions necessary for a Global Protect or Global Unprotect to be Atmel AT25DF161 for command 21 ...
Page 22
... Status Register to change the SPRL bit from a logical “1” logical “0” provided the WP pin is deasserted. Likewise, the system can write an F0h to change the SPRL bit from a logical “0” Atmel AT25DF161 22 Bit Protection Operation Global Unprotect – ...
Page 23
... Figure 9-5. Read Sector Protection Register CS SCK SI SO 3687E–DFLASH–11/10 and Table 11-1 on page 30 , the first byte of data output will not be valid. Therefore, if operating at clock frequencies CLK Atmel AT25DF161 for details on the Status Register format and what “Read Status 23 ...
Page 24
... Hardware 0 1 Locked 1 0 Software 1 1 Locked Atmel AT25DF161 24 Sector Protection Register ( SPRL Change Allowed Sector Protection Registers Unlocked and modifiable using the Protect and Unprotect Sector Can be modified from commands. Global Protect and Unprotect can also be performed. Locked in current state. Protect and Unprotect Sector commands Locked will be ignored ...
Page 25
... CS pin has been deasserted. 3687E–DFLASH–11/10 34). To issue the Sector Lockdown command, the CS pin must first addition, the WEL bit in the Status Register will be reset LOCK Atmel AT25DF161 “Freeze Sector Lockdown 25 ...
Page 26
... When the device aborts the Freeze Sector Lockdown State operation, the WEL bit in the Status Register will be reset to a logical “0”; however, the state of the SLE bit will be unchanged. Figure 10-2. Freeze Sector Lockdown State CS SCK SI SO Atmel AT25DF161 26 3687E–DFLASH–11/10 ...
Page 27
... The remaining 64-bytes of the OTP Security Register (byte locations 64 through 127) are factory ® programmed by Atmel and will contain a unique value for each device. The factory programmed data is fixed and cannot be changed. 3687E–DFLASH–11/10 , the first byte of data output will not be valid. Therefore, if operating at clock frequencies CLK Atmel AT25DF161 27 ...
Page 28
... WEL bit in the Status Register will be reset back to the logical “0” state. If the device is powered-down during the OTP Security Register program cycle, then the contents of the 64-byte user programmable portion of the OTP Security Register cannot be guaranteed and cannot be programmed again. Atmel AT25DF161 28 Security Register ...
Page 29
... Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Figure 10-5. Read OTP Security Register CS SCK SI SO 3687E–DFLASH–11/ read the OTP Security Register, the CS pin must first be asserted and the opcode of MAX Atmel AT25DF161 29 ...
Page 30
... Notes: 1. Only bit 7 of Status Register Byte 1 will be modified when using the Write Status Register Byte 1 command 2. R/W = Readable and writeable R = Readable only Atmel AT25DF161 30 , the first two bytes of data output from the Status Register will not be valid. Therefore, if CLK , at least four bytes of data must be clocked out from the device in order to read ...
Page 31
... R/W Sector Lockdown and Freeze Sector Lockdown State 1 commands are enabled 0 No sectors are program suspended (default sector is program suspended 0 No sectors are erase suspended (default sector is erase suspended 0 Device is ready R 1 Device is busy with an internal operation Atmel AT25DF161 31 ...
Page 32
... SLE bit is in the logical “0” state (the default state after power-up), the Sector Lockdown and Freeze Sector Lockdown commands are disabled. If the Sector Lockdown and Freeze Sector Lockdown commands are disabled, then any attempts to issue the commands will be ignored. This provides a safeguard for these commands against accidental or erroneous Atmel AT25DF161 32 3687E–DFLASH–11/10 ...
Page 33
... The complete one byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the state of 3687E–DFLASH–11/10 “Global Protect/Unprotect” on page 21 Atmel AT25DF161 for more details. 33 ...
Page 34
... RSTE and SLE bits will not change, and the WEL bit in the Status Register will be reset back to the logical “0” state. Table 11-4. Write Status Register Byte 2 Format Bit 7 Bit Atmel AT25DF161 34 Bit 5 Bit 4 Bit 3 Global Protect/Unprotect Table Bit 5 ...
Page 35
... The complete opcode and confirmation byte must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no Reset operation will be performed. 3687E–DFLASH–11/10 Atmel AT25DF161 . Since the program or erase RST 35 ...
Page 36
... The CS pin can be deasserted at any time and does not require that a full byte of data be read. Table 12-1. Manufacturer and Device ID Information Byte No. Data Type 1 Manufacturer ID 2 Device ID (Part 1) 3 Device ID (Part 2) 4 Extended Device Information String Length Atmel AT25DF161 36 . Since not all Flash devices CLK Value 1Fh 46h 02h 00h 3687E–DFLASH–11/10 ...
Page 37
... Density Code Product Version Code shown for SI and SO represents one byte (8 bits) Atmel AT25DF161 Hex Bit 0 Value Details 1Fh JEDEC Code: 0001 1111 (1Fh for Atmel) 1 Family Code: 010 (AT25DF/26DFxxx series) 46h Density Code: 00110 (16-Mbit) 0 Sub Code: 000 (Standard series) ...
Page 38
... If the complete opcode is not clocked in before the CS pin is deasserted the CS pin is not deasserted on an even byte boundary (multiples of eight bits), then the device will abort the operation and return to the Deep Power-Down mode. Atmel AT25DF161 38 and return to the standby mode. After the RDPD 3687E– ...
Page 39
... If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state. 3687E–DFLASH–11/10 Atmel AT25DF161 39 ...
Page 40
... SCK to latch the data in. Similarly, the host controller should clock its data out on the rising edge of SCK in order to give the AT25DF161 a full clock cycle to latch the incoming data in on the next rising edge of SCK. ...
Page 41
... In an effort to continue our goal of maintaining world-class quality leadership, Atmel testing on the Atmel AT25DF161 that would not normally be done with a Serial Flash device. The testing that has been performed on the AT25DF161 involved extensive, non-stop reading of the memory array on pre-conditioned devices. The pre-conditioning of the devices, which entailed erasing and programming the entire memory array 10,000 times, was done to simulate a customer environment and to exercise the memory cells to a certain degree ...
Page 42
... IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH Atmel AT25DF161 42 *NOTICE: + 0.5V CC Atmel AT25DF161 (2.3V Version) Ind. -40°C to 85°C 2.3V to 3.6V Condition CS, WP, HOLD = all inputs at CMOS levels CS, WP, HOLD = all inputs at CMOS levels f = 100MHz 0mA; ...
Page 43
... HOLD Low to Output High-Z HLQZ (1) t HOLD High to Output Low-Z HHQX (1)(3) t Write Protect Setup Time WPS (1)(3) t Write Protect Hold Time WPH 3687E–DFLASH–11/10 Atmel AT25DF161 Atmel Atmel AT25DF161 AT25DF161 (2.3V Version) Min Max Min Max Units 100 100 MHz 85 ...
Page 44
... Not 100% tested (value guaranteed by design and characterization) 15.7 Power-up Conditions Symbol Parameter t Minimum V to Chip Select Low Time VCSL CC t Power-up Device Delay Before Program or Erase Allowed PUW V Power-on Reset Voltage POR Atmel AT25DF161 44 Atmel AT25DF161 AT25DF161 (2.3V Version) Min Max Min 20 20 200 Min Typ 1 ...
Page 45
... Input Test Waveforms and Measurement Levels 0. DRIVING LEVELS 0. < (10 15.9 Output Test Load DEVICE UNDER TEST 15pF (frequencies above 70MHz) or 30pF 16. AC Waveforms Figure 16-1. Serial Input Timing CS SCK SI SO Figure 16-2. Serial Output Timing CS SCK SI SO 3687E–DFLASH–11/ MEASUREMENT CC LEVEL Atmel AT25DF161 45 ...
Page 46
... Figure 16-3. WP Timing for Write Status Register Byte 1 Command When SPRL = SCK SI SO Figure 16-4. HOLD Timing – Serial Input CS SCK HOLD SI SO Figure 16-5. HOLD Timing – Serial Output CS SCK HOLD SI SO Atmel AT25DF161 46 3687E–DFLASH–11/10 ...
Page 47
... Atmel Designator Product Family Device Density 16 = 16-megabit Interface 1 = Serial 17.2 Green Package Options (Pb/Halide-free/RoHS Compliant) Atmel Ordering Code AT25DF161-MH-Y AT25DF161-MH-T AT25DF161-SSH-B AT25DF161-SSH-T AT25DF161-SH-B AT25DF161-SH-T AT25DF161-MHF-Y AT25DF161-MHF-T AT25DF161-SSHF-B AT25DF161-SSHF-T AT25DF161-SHF-B AT25DF161-SHF-T Note: The shipping carrier option code is not marked on the devices 8MA1 8-pad ( ...
Page 48
... K 8 Pin #1 Notch (Option Bottom View L Notes: 1. This package conforms to JEDEC reference MO-229, Saw Singulation 2. The terminal # Laser-marked Feature Package Drawing Contact: packagedrawings@atmel.com Atmel AT25DF161 Option A 1 (0. TITLE 8MA1, 8-pad ( 0.6mm Body), Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN) ...
Page 49
... Top View Side View TITLE 8S1, 8-lead, (0.150” Wide Body), Plastic Gull Wing Outline (JEDEC SOIC) Atmel AT25DF161 E1 L Ø End View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 1.35 – 1.75 A1 0.10 – 0.25 0.51 b 0.31 – ...
Page 50
... Mismatch of the upper and lower dies and resin burrs are not included. 3. Determines the true geometric position. 4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. Package Drawing Contact: packagedrawings@atmel.com Atmel AT25DF161 Top View ...
Page 51
... Changed Deep Power-Down Current values – Increased typical value from 1µA to 5µA – Increased maximum value from 5µA to 10µA Table 6-1 Corrected clock frequency values in Added System Considerations section Remove Preliminary and update template Added 2.3V to 3.6V operating range Atmel AT25DF161 51 ...
Page 52
... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...