C8051F045R Silicon Labs, C8051F045R Datasheet - Page 69
![no-image](/images/no-image-200.jpg)
C8051F045R
Manufacturer Part Number
C8051F045R
Description
8-bit Microcontrollers - MCU 25 MIPS 64KB 10ADC
Manufacturer
Silicon Labs
Datasheet
1.C8051F044R.pdf
(328 pages)
Specifications of C8051F045R
Product Category
8-bit Microcontrollers - MCU
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
64 KB
Data Ram Size
4.25 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 3.6 V
Package / Case
TQFP-64
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
13
Data Rom Size
64 KB
Interface Type
CAN, SMBus, SPI, UART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
32
Number Of Timers
16 bit
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
500
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
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6.
The ADC0 subsystem for the C8051F042/3/4/5/6/7 consists of a 9-channel, configurable analog multi-
plexer (AMUX0), a programmable gain amplifier (PGA0), and a 100 ksps, 10-bit successive-approxima-
tion-register ADC with integrated track-and-hold and Programmable Window Detector (see block diagram
in Figure 6.1). The AMUX0, PGA0, Data Conversion Modes, and Window Detector are all configurable
under software control via the Special Function Registers shown in Figure 6.1. The voltage reference used
by ADC0 is selected as described in
C8051F042/4/6 devices, or
C8051F043/5/7 devices. The ADC0 subsystem (ADC0, track-and-hold and PGA0) is enabled only when
the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is in low
power shutdown when this bit is logic 0.
6.1.
The analog multiplexer can input analog signals to the ADC from four external analog input pins, Port 3
port pins (optionally configured as analog input pins), High Voltage Difference Amplifier, and an internally
connected on-chip temperature sensor (temperature transfer function is shown in Figure 6.6). AMUX input
pairs can be programmed to operate in either differential or single-ended mode. This allows the user to
select the best measurement technique for each input channel, and even accommodates mode changes
"on-the-fly". The AMUX defaults to all single-ended inputs upon reset. There are three registers associated
with the AMUX: the Channel Selection register AMX0SL (SFR Definition 6.2), the Configuration register
AMX0CF (SFR Definition 6.1), and the Port Pin Selection register AMX0PRT (SFR Definition 6.3).
Table 6.1 shows AMUX functionality by channel for each possible configuration. The PGA amplifies the
AMUX output signal by an amount determined by the states of the AMP0GN2-0 bits in the ADC0 Configu-
ration register, ADC0CF (SFR Definition 6.5). The PGA can be software-programmed for gains of 0.5, 2, 4,
8 or 16. Gain defaults to unity on reset.
AGND
10-Bit ADC (ADC0, C8051F042/3/4/5/6/7 Only)
I/O Pins
Analog Multiplexer and PGA
Analog
Port 3
Input
Input
Pins
HV
SENSOR
TEMP
AMX0CF
ADC0GTH
Figure 6.1. 10-Bit ADC0 Functional Block Diagram
AMUX
(SE or
9-to-1
DIFF)
AMX0SL
Section “10. Voltage Reference (C8051F041/3/5/7)” on page 117
ADC0GTL
X
Section “9. Voltage Reference (C8051F040/2/4/6)” on page 113
+
-
AV+
AD0EN
AGND
ADC0CF
ADC0LTH
Rev. 1.5
C8051F040/1/2/3/4/5/6/7
ADC
10-Bit
AV+
SAR
ADC0CN
ADC0LTL
Start Conversion
10
20
10
Comb.
00
01
10
11
Logic
AD0BUSY (W)
Timer 3 Overflow
CNVSTR0
Timer 2 Overflow
AD0WINT
for
for
69
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