C8051F045R Silicon Labs, C8051F045R Datasheet - Page 133

• Manufacturer Part Number: C8051F045R
• Description: 8-bit Microcontrollers - MCU 25 MIPS 64KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F045R

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4.25 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 13
• Data Rom Size: 64 KB
• Interface Type: CAN, SMBus, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

12.2. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. There are 256 bytes of internal data
memory and 64k bytes of internal program memory address space implemented within the CIP-51. The
CIP-51 memory organization is shown in Figure 12.2.
12.2.1. Program Memory
The CIP-51 has a 64 kB program memory space. The MCU implements 64 kB (C8051F040/1/2/3/4/5) and
32 kB (C8051F046/7) of this program memory space as in-system re-programmed Flash memory, orga-
nized in a contiguous block from addresses 0x0000 to 0xFFFF (C8051F040/1/2/3/4/5) and 0x0000 to
0x7FFF (C8051F046/7). Note: 512 bytes from 0xFE00 to 0xFFFF (C8051F040/1/2/3/4/5 only) of this mem-
ory are reserved for factory use and are not available for user program storage.
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature pro-
vides a mechanism for the CIP-51 to update program code and use the program memory space for non-
volatile data storage. Refer to
0x1007F
0x10000
0x1007F
0x10000
0xFDFF
0xFE00
0x7FFF
0x0000
0x8000
0x0000
PROGRAM/DATA MEMORY
Programmable in 512
Programmable in 512
C8051F040/1/2/3/4/5
Scrachpad Memory
Scrachpad Memory
Byte Sectors)
C8051F046/7
Byte Sectors)
(DATA only)
RESERVED
(DATA only)
RESERVED
(In-System
(In-System
(FLASH)
64 kB
Flash
32 kB
Flash
Section “15. Flash Memory” on page 179
Figure 12.2. Memory Map
0xFFFF
0x0FFF
0x1000
0x0000
0xFF
0x7F
0x2F
0x1F
0x80
0x30
0x20
0x00
XRAM - 4096 Bytes
(accessable using MOVX
(Indirect Addressing
(Direct and Indirect
Off-chip XRAM space
INTERNAL DATA ADDRESS SPACE
EXTERNAL DATA ADDRESS SPACE
General Purpose
Upper 128 RAM
Bit Addressable
Rev. 1.5
Addressing)
instruction)
Registers
Only)
DATA MEMORY (RAM)
C8051F040/1/2/3/4/5/6/7
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
Special Function
Registers
for further details.
0
256 SFR Pages
1
2
Up To
3
F
133