MC68HC908GR8CD Freescale Semiconductor, MC68HC908GR8CD Datasheet - Page 169

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MC68HC908GR8CD

Manufacturer Part Number
MC68HC908GR8CD
Description
8-bit Microcontrollers - MCU 8 Bit 8MHz
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68HC908GR8CD

Product Category
8-bit Microcontrollers - MCU
Rohs
yes
Core
HC08
Data Bus Width
8 bit
Maximum Clock Frequency
8 MHz
Program Memory Size
64 KB
Data Ram Size
384 B
Operating Supply Voltage
3 V to 5 V
Package / Case
SOIC-28
Mounting Style
SMD/SMT
Data Rom Size
64 KB
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
21
Program Memory Type
Flash
18.4.3.2 Character Reception
During an SCI reception, the receive shift register shifts characters in from the PE1/RxD pin. The SCI data
register (SCDR) is the read-only buffer between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data portion of the character transfers
to the SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that
the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the
SCRF bit generates a receiver CPU interrupt request.
18.4.3.3 Data Sampling
The receiver samples the PE1/RxD pin at the RT clock rate. The RT clock is an internal signal with a
frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at
the following times (see
To locate the start bit, data recovery does an asynchronous search for a 0 preceded by three 1s. When
the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.
Table 18-2
Freescale Semiconductor
PE1/RxD
RT CLOCK
RT CLOCK
After every start bit
After the receiver detects a data bit change from 1 to 0 (after the majority of data bit samples at
RT8, RT9, and RT10 returns a valid 1 and the majority of the next RT8, RT9, and RT10 samples
returns a valid 0)
SAMPLES
CLOCK
RESET
STATE
RT
summarizes the results of the start bit verification samples.
RT3, RT5, and RT7 Samples
Figure
000
001
010
011
100
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
QUALIFICATION
18-6):
Figure 18-6. Receiver Data Sampling
START BIT
Table 18-2. Start Bit Verification
VERIFICATION
START BIT
Verification
Start Bit
Yes
Yes
Yes
Yes
No
START BIT
SAMPLING
DATA
Noise Flag
0
1
1
0
1
Functional Description
LSB
169

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