MC68HC908GR8CD Freescale Semiconductor, MC68HC908GR8CD Datasheet

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MC68HC908GR8 MC68HC908GR4 Data Sheet M68HC08 Microcontrollers MC68HC908GR8 Rev. 7 10/2006 freescale.com ...

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... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2006. All rights reserved. ...

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... MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev Freescale Semiconductor ...

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... Chapter 19 System Integration Module (SIM 187 Chapter 20 Serial Peripheral Interface (SPI 205 Chapter 21 Timebase Module (TBM 225 Chapter 22 Timer Interface Module (TIM 229 Chapter 23 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Chapter 24 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Chapter 25 Ordering Information 281 MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor 5 ...

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... List of Chapters MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev Freescale Semiconductor ...

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... Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.7 Vector Addresses 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.1.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.1.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2 Analog-to-Digital Converter (ADC 3.2.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Chapter 1 General Description and and DDA SSA /V DDAD REFH Chapter 2 Memory Map Chapter 3 ...

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... Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.14 Exiting Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2.1 Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2.3 Internal Reset 4.2.3.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.2.3.2 COP Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.2.3.3 Low-Voltage Inhibit Reset 4.2.3.4 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2.3.5 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2.4 SIM Reset Status Register MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev Chapter 4 Resets and Interrupts Freescale Semiconductor ...

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... ADC Voltage In (V ADIN 5.7 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.7.1 ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.7.2 ADC Data Register 5.7.3 ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (ADC) )/ADC Voltage Reference High Pin (V DDAD )/ADC Voltage Reference Low Pin (V SSAD ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REFH ) . . . . . . . . . . . 58 ...

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... CGMC Base Clock Output (CGMOUT 7.4.10 CGMC CPU Interrupt (CGMINT 7.5 CGMC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.5.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.5.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.5.3 PLL Multiplier Select Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev Chapter 6 Break Module (BRK) Chapter 7 Clock Generator Module (CGMC DDA ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 SSA Freescale Semiconductor ...

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... Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 10.1 Features 10.2 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10.2.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 10.2.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 10.2.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Chapter 8 Configuration Register (CONFIG) Chapter 9 Computer Operating Properly (COP) Chapter 10 Central Processing Unit (CPU) 11 ...

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... Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.6 Keyboard Module During Break Interrupts 123 13.7 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 13.7.1 Keyboard Status and Control Register 124 13.7.2 Keyboard Interrupt Enable Register 125 MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev Chapter 11 Flash Memory Chapter 12 External Interrupt (IRQ) Chapter 13 Keyboard Interrupt (KBI) Freescale Semiconductor ...

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... Port C Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 16.5 Port 152 16.5.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 16.5.2 Data Direction Register 153 16.5.3 Port D Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Chapter 14 Low-Voltage Inhibit (LVI) Chapter 15 Monitor ROM (MON) Chapter 16 Input/Output Ports (I/O) 13 ...

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... PE2/TxD (Transmit Data 174 18.7.2 PE1/RxD (Receive Data 175 18.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 18.8.1 SCI Control Register 175 18.8.2 SCI Control Register 177 18.8.3 SCI Control Register 179 18.8.4 SCI Status Register 180 18.8.5 SCI Status Register 182 MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev Chapter 17 Random-Access Memory (RAM) Chapter 18 Freescale Semiconductor ...

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... SIM Break Status Register 201 19.7.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 19.7.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 20.2 Features 205 20.3 Pin Name Conventions and I/O Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Chapter 19 System Integration Module (SIM) Chapter 20 Serial Peripheral Interface (SPI) 15 ...

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... Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 21.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 21.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 21.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 21.6 Timebase Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 22.2 Features 229 22.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev Chapter 21 Timebase Module (TBM) Chapter 22 Timer Interface Module (TIM) Freescale Semiconductor ...

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... CGM Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 23.9 Output High-Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 23.10 Output Low-Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 23.11 Typical Supply Currents 261 23.12 ADC Characteristics 263 23.13 5.0 V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 23.14 3.0 V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 23.15 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 23.16 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Chapter 23 Electrical Specifications 17 ...

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... Table of Contents 24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 25.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 25.3 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Revision History 283 MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev Chapter 24 Mechanical Specifications Chapter 25 Ordering Information Revision History Freescale Semiconductor ...

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... Wait mode – Stop mode • Master reset pin and power-on reset (POR security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor (1) 19 ...

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... Memory-to-memory data transfers Fast 8 × 8 multiply instruction • • Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev Freescale Semiconductor ...

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... V SSA † Ports are software configurable with pullup device if input port. ‡ Higher current drive port pins * Pin contains integrated pullup device MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor INTERNAL BUS PROGR. TIMEBASE MODULE SINGLE BRKPT BREAK MODULE DUAL V. LOW-VOLTAGE INHIBIT ...

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... N. Figure 1-2. SDIP Pin Assignments PTC1 PTC0 N. N.C. PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 V /V SSAD REFL V /V DDAD REFH N.C. N.C. PTB5/AD5 PTB4/AD4 PTB3/AD3 V SS PTB2/AD2 PTB1/AD1 PTB0/AD0 PTD6/T2CH0 Freescale Semiconductor ...

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... NOTE: Ports PTB4, PTB5, PTC0, and PTC1 are available only with the QFP. OTE: Ports PTB4, PTB5, PTC0, and PTC1 are available only with the QFP. Figure 1-4. DIP And SOIC Pin Assignments MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor ...

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... Decoupling of these pins should be as per the digital supply. See (CGMC). MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev and MCU 0.1 μ Figure 1-5. Power Supply Bypassing Chapter 12 External Interrupt and V ) DDA SSA Figure 1 Chapter 7 Clock Chapter 4 (IRQ). Chapter 7 Clock Generator Module Freescale Semiconductor ...

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... PTD6–PTD4 can be individually programmed to be timer interface module (TIM1 and TIM2) pins. See Peripheral Interface (SPI), and See MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor /V DDAD REFH NOTE and have the same potential as V ...

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... Any unused inputs and I/O ports should be tied to an appropriate logic level (either require termination, termination is recommended to reduce the possibility of electro-static discharge damage. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev Chapter 18 Serial Communications Interface (SCI) (I/O). NOTE ). Although the I/O ports of the MC68HC908GR8 do not SS and Freescale Semiconductor ...

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... LVI status register, LVISR • $FF7E; FLASH block protect register, FLBPR Data registers are shown in Figure MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor 2-1) and in register figures in this document, unimplemented 2-2, and Table 2 list of vector locations. Figure 2-1, includes: Figure 2-1 ...

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... Break Address Register High (BRKH) Break Address Register Low (BRKL) Break Status and Control Register (BRKSCR) LVI Status Register (LVISR) Figure 2-1. Memory Map 64 Bytes RAM 384 Bytes 544 Bytes MC68HC908GR4 Unimplemented 3584 Bytes MC68HC908GR4 FLASH Memory 4096 Bytes Reserved Continued on next page Freescale Semiconductor ...

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... Reset: Read: Port D Data Register $0003 Write: (PTD) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor ↓ Unimplemented ↓ Reserved for Compatibility with Monitor Code for A-Family Parts Monitor ROM ↓ Unimplemented ↓ ...

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... DDRD0 PTE1 PTE0 DDRE1 DDRE0 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 PTCPUE1 PTCPUE0 CPHA SPWOM SPE SPTIE SPTE MODFEN SPR1 SPR0 Unaffected Freescale Semiconductor ...

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... Time Base Module Control $001C Write: Register (TBCR) Reset: Read: IRQ Status and Control $001D Write: Register (INTSCR) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Bit ...

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... Bit Bit Bit Bit ELS0B ELS0A TOV0 CH0MAX Bit Bit 0 ELS1B ELS1A TOV1 CH1MAX Bit Unaffected Freescale Semiconductor ...

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... PLL Control Register $0036 Write: (PCTL) Reset: Read: PLL Bandwidth Control $0037 Write: Register (PBWC) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Bit Bit Indeterminate after reset TOF 0 TOIE ...

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... VRS0 RDS3 RDS2 RDS1 RDS0 ADCH3 ADCH2 ADCH1 ADCH0 AD3 AD2 AD1 AD0 NOTE ILAD MODRST LVI Unaffected Freescale Semiconductor ...

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... Write: Register (FLBPR) † Reset: Read: COP Control Register $FFFF Write: (COPCTL) Reset: † Non-volatile FLASH register Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Bit IF6 IF5 IF4 IF3 ...

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... TIM1 Channel 0 Vector (Low) $FFF8 PLL Vector (High) IF2 $FFF9 PLL Vector (Low) $FFFA IRQ Vector (High) IF1 $FFFB IRQ Vector (Low) $FFFC SWI Vector (High) — $FFFD SWI Vector (Low) $FFFE Reset Vector (High) — $FFFF Reset Vector (Low) Vector Freescale Semiconductor ...

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... The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one conversion cycle to stabilize the analog circuitry. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Chapter 8 Configuration Register Chapter 8 Configuration 37 ...

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... CGM (oscillator and phase-locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and CGMINT). If the OSCSTOPEN bit in the CONFIG register is set, then the phase locked loop is shut off, but the oscillator will continue to operate in stop mode. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev Freescale Semiconductor ...

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... Low-Voltage Inhibit Module (LVI) 3.9.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Computer Operating Properly Module (COP) 39 ...

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... The TIM remains active in wait mode. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev Freescale Semiconductor ...

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... Upon exit from stop mode, the system clocks begin running after an oscillator stabilization delay. A 12-bit stop recovery counter inhibits the system clocks for 4096 CGMXCLK cycles after the reset or external interrupt. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Timebase Module (TBM) voltage resets the MCU tripf ...

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... The short stop recovery bit, SSREC, in the configuration register controls the oscillator stabilization delay during stop recovery. Setting SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32 CGMXCLK cycles. Use the full stop recovery time (SSREC = 0) in applications that use an external crystal. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev NOTE Freescale Semiconductor ...

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... All internal reset sources pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external devices. The MCU is held in reset for an additional 32 CGMXCLK cycles after releasing the RST pin. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor , generates an external reset. An external reset sets the IRL ...

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... To clear the COP counter and prevent a COP reset, write any value to the COP control register at location $FFFF. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev 4096 32 32 CYCLES CYCLES CYCLES Figure 4-1. Power-On Reset Recovery pin the POR must DD DD Freescale Semiconductor ...

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... Only a read of the SIM reset status register clears all reset flags. After multiple resets from different sources without reading the register, multiple flags remain set. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor TRIPF is below V and during the oscillator stabilization DD ...

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... MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev PIN COP ILOP ILAD Unimplemented 2 1 Bit 0 MODRST LVI Freescale Semiconductor ...

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... CONDITION CODE REGISTER 5 4 INDEX REGISTER (LOW BYTE)* 3 STACKING ORDER PROGRAM COUNTER (HIGH BYTE) 2 PROGRAM COUNTER (LOW BYTE) 1 *High byte of index register is not stacked. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor • • • 1 ACCUMULATOR 2 3 UNSTACKING ORDER 4 5 • ...

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... H register or uses the indexed addressing mode, save the H register and then restore it prior to exiting the routine. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev CLI LDA #$FF PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI . Interrupt Recognition Example NOTE BACKGROUND ROUTINE Freescale Semiconductor ...

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... Keyboard pin ADC conversion complete Timebase 1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction highest priority MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Table 4-1. Interrupt Sources INT Register (1) Flag Mask ...

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... I BIT SET? I BIT SET? NO YES IRQ INTERRUPT ? NO YES CGM INTERRUPT ? NO OTHER YES INTERRUPTS ? NO STACK CPU REGISTERS LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION ? NO RTI YES UNSTACK CPU REGISTERS INSTRUCTION ? NO EXECUTE INSTRUCTION Figure 4-5. Interrupt Processing SET I BIT Freescale Semiconductor ...

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... The SPI transmit interrupt enable bit, SPTIE, enables SPTE CPU interrupt requests. SPTE is in the SPI status and control register and SPTIE is in the SPI control register. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Interrupts 51 ...

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... Parity error bit (PE) — set when the SCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, enables PE to generate SCI error CPU interrupt requests SCI status register 1. PEIE is in SCI control register 3. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev Freescale Semiconductor ...

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... TIM2 overflow SPI receive SPI transmit SCI error SCI receive SCI transmit Keyboard ADC conversion complete Timebase MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Table 4-2. Interrupt Source Flags Interrupt Status Register Flag Interrupts Table 4-2 summarizes the — — IF1 IF2 ...

Page 54

... IF11 IF10 Bit 0 IF1 Table 4- Bit 0 IF9 IF8 Table 4- Bit 0 0 IF16 IF15 Table 4-2. Freescale Semiconductor ...

Page 55

... DDR will not have any affect on the port pin that is selected by the ADC. Read of a port pin in use by the ADC will return the corresponding DDR bit the DDR bit the value in the port data latch is read. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor ). ADIN 55 ...

Page 56

... ADC converts the signal to $FF (full scale). If the REFH NOTE ; and V is connected to the ADC analog DDAD REFL should be tied to the same potential as V DDAD DISABLE PTBx ADC CHANNEL x DISABLE ADC ADCH4–ADCH0 (V ) ADIN CHANNEL SELECT and V REFH REFL . REFH is connected to the REFH via DD Freescale Semiconductor are a ...

Page 57

... The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the analog circuitry before attempting a new ADC conversion after exiting stop mode. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor 23.12 ADC Characteristics ADC Clock Cycles ...

Page 58

... Voltage Reference Low Pin (V SSAD as its ground pin. Connect the V SSAD ) AIEN ADCO ADCH4 ADCH3 REFH pin to the same voltage DDAD for good results. DDAD ) REFL pin to the same voltage SSAD 2 1 Bit 0 ADCH2 ADCH1 ADCH0 Freescale Semiconductor ...

Page 59

... NOTE unknown channel is selected it should be made clear what value the user will read from the ADC Data Register, unknown or reserved is not specific enough. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Table 5-1. NOTE Table 5-1. Mux Channel Select ADCH2 ADCH1 ...

Page 60

... ADC Clock Rate ADC input clock ÷ ADC input clock ÷ ADC input clock ÷ ADC input clock ÷ ADC input clock ÷ Bit 0 AD2 AD1 AD0 Bit Freescale Semiconductor ...

Page 61

... As long as the internal ADC clock is at approximately 1 MHz, correct operation can be guaranteed Internal bus clock 0 = External clock (CGMXCLK) During the conversion process, changing the ADC clock will result in an incorrect conversion. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor fxclk or bus frequency = 1 MHz ADIV2–ADIV0 NOTE I/O Registers 61 ...

Page 62

... Analog-to-Digital Converter (ADC) MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev Freescale Semiconductor ...

Page 63

... MCU to normal operation. 6.3.1 Flag Protection During Break Interrupts The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Figure 6-1 shows the structure of the break module. 63 ...

Page 64

... BRKE BRKA Unimplemented Figure 6-2. I/O Register Summary CONTROL BREAK NOTE Reserved Freescale Semiconductor Bit Bit 8 0 Bit ...

Page 65

... This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit Breaks enabled on 16-bit address match 0 = Breaks disabled on 16-bit address match MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor is present on the RST pin. TST Chapter 3 Low-Power 6 ...

Page 66

... Reserved 2 1 Bit Bit Bit Bit Bit NOTE Freescale Semiconductor ...

Page 67

... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor ...

Page 68

... Break Module (BRK) MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev Freescale Semiconductor ...

Page 69

... Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives the system clocks from either CGMOUT or CGMXCLK. Figure 7-1 shows the structure of the CGMC. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor 69 ...

Page 70

... VRS7–VRS0 VOLTAGE LOOP CONTROLLED FILTER OSCILLATOR PLL ANALOG AUTOMATIC INTERRUPT MODE CONTROL CONTROL AUTO ACQ PLLIE PRE1–PRE0 FREQUENCY DIVIDER Figure 7-1. CGMC Block Diagram CGMXCLK (TO: SIM, TIMEBASE, ADC) CLOCK SELECT ³ 2 CIRCUIT CGMVCLK PLLF Freescale Semiconductor CGMOUT (TO SIM) CGMINT (TO SIM) ...

Page 71

... P and the modulo divider reduces the VCO clock by a factor, N. The dividers’ output is the VCO feedback clock, CGMVDV, running at a frequency, f 7.3.6 Programming the PLL for more information.) MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor , (38.4 kHz) times a linear factor, L, and a power-of-two factor VCLK Functional Description . Modulating the voltage on the ...

Page 72

... MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev Modes. The value of the external capacitor and the 7.5.2 PLL Bandwidth Control 7.3.8 Base Clock Selector Circuit.) The PLL is automatically in 7.3.8 Base Clock Selector Register read-only indicator of the mode of the Modes.) 7.8 Acquisition/Lock Time Specifications Register.) 7.5.2 PLL Circuit.) If for Freescale Semiconductor ...

Page 73

... See Specifications. Choose the reference divider After choosing N and P, the actual bus frequency can be determined using equation in 2 above. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor 7.8 Acquisition/Lock Time Specifications Register.) Specifications), after turning on the PLL by setting PLLON in the PLL ...

Page 74

... NOM ⎛ ⎞ f VCLK ⎜ ⎟ -------------------------- L = round ⎝ E ⎠ × NOM to an integer divisor of f RCLK ⎛ ⎞ ⎫ f VCLKDES ⎜ ⎟ ⎬ ------------------------- - ⎝ f ⎠ ⎭ RCLK ⎞ ⎟ ⎠ and f . VCLK BUS Freescale Semiconductor , BUSDES ...

Page 75

... In the PLL reference divider select register (PMDS), program the binary coded equivalent of R. Table 7-1 provides numeric examples (numbers are in hexadecimal notation): f BUS 2.0 MHz 2.4576 MHz 2.5 MHz 4.0 MHz 4.9152 MHz 5.0 MHz 7.3728 MHz 8.0 MHz MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor E ( × VRS NOM E × NOM ≤ ...

Page 76

... Routing should be done with great care to minimize signal cross talk and noise. See 23.8.1 CGM Component Specifications MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev 7.3.6 Programming the PLL Circuit.) for capacitor and resistor values. does not account for three possible Figure Freescale Semiconductor 7-2. ...

Page 77

... Figure To prevent noise problems, the filter network should be placed as close to the CGMXFC pin as possible, with minimum routing distances and no routing of other signals across the network. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor CGMXCLK CGMXFC OSC2 ...

Page 78

... CGMINT is the interrupt signal generated by the PLL lock detector. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev DDA NOTE ) SSA NOTE Figure 7-2 shows only the logical relation of CGMXCLK to OSC1 pin to the same voltage DDA pin to the same voltage SSA ) and comes XCLK Freescale Semiconductor ...

Page 79

... When AUTO = 1, ACQ is read-only. 4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only. 5. When PLLON = 1, the PLL programming register is read-only. 6. When BCS = 1, PLLON is forced set and is read-only. Figure 7-3. CGMC I/O Register Summary MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Register.) High.) Low.) Register.) Register.) ...

Page 80

... VCO clock as the source of the base clock MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev PLLF PLLON BCS PRE1 Figure 7-4. PLL Control Register (PCTL) NOTE NOTE 2 1 Bit 0 PRE0 VPR1 VPR0 7.3.8 Base Clock Selector 7.3.8 Base Clock Freescale Semiconductor ...

Page 81

... PLLON bit is set. Reset clears these bits. Table 7-3. VPR1 and VPR0 Programming VPR1 and VPR0 not program value of 3. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Circuit.) PLL.) PRE1 and PRE0 cannot be written when the NOTE ...

Page 82

... Reset clears this bit, enabling acquisition mode Tracking mode 0 = Acquisition mode MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev LOCK 0 0 ACQ Reserved 2 1 Bit Freescale Semiconductor ...

Page 83

... Reset initializes the register to $40 for a default multiply value of 64. The multiplier select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor ...

Page 84

... VRS7–VRS0 cannot be written when the PLLON bit in the VRS Exceptions.) A value of $00 in the VCO range select Exceptions.). Reset initializes the register to $40 NOTE NOTE RDS3 Bit 0 VRS2 VRS1 VRS0 Register), controls the 7.3.8 Base 2 1 Bit 0 RDS2 RDS1 RDS0 Freescale Semiconductor ...

Page 85

... WAIT exit. This would be the case also when the PLL is to wake the MCU from wait mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor 7.3.6 Programming the PLL.) RDS7–RDS0 cannot be written when the 7 ...

Page 86

... Minor errors may not even be registered. Typical PLL applications prefer to use this definition because the system requires the output frequency to be within a certain tolerance of the desired frequency regardless of the size of the initial error. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev 19.7.3 SIM Break Flag Control Register.) Freescale Semiconductor ...

Page 87

... For reference frequencies between the values listed in the table, extrapolate to the nearest common capacitor value. In general, a slightly larger capacitor provides more stability at the expense of increased lock time. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor 7.3.3 PLL Circuits, Register.) 7.8.3 Choosing a ...

Page 88

... Figure 7-10. PLL Filter 0.15 μ 0.12 μ 0.10 μ SSA C F 0.22 μF 0.18 μF 0.18 μF 0.12 μF 0.12 μF 0.1 μF 0.1 μ Freescale Semiconductor ...

Page 89

... FLASH memory but are special registers containing one-time writeable latches after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Address: $001E Bit 7 Read: 0 Write: Reset Unimplemented Figure 8-1. Configuration Register 2 (CONFIG2) MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor NOTE NOTE Figure 8-1 and ...

Page 90

... MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev LVISTOP LVIRSTD LVIPWRD LVI5OR3 See Note Chapter 14 Low-Voltage Inhibit 2 1 Bit 0 SSREC STOP COPD Chapter 9 Computer Operating Chapter 14 Low-Voltage Inhibit (LVI). Chapter 14 Low-Voltage Inhibit . See Chapter 23 DD Freescale Semiconductor (LVI). ...

Page 91

... STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD — COP Disable Bit COPD disables the COP module. See 1 = COP module disabled 0 = COP module enabled MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor NOTE Chapter 9 Computer Operating Properly (COP) Functional Description 91 ...

Page 92

... Configuration Register (CONFIG) MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev Freescale Semiconductor ...

Page 93

... COPEN (FROM SIM) COP DISABLE (FROM CONFIG) RESET COPCTL WRITE COP RATE SEL (FROM CONFIG) MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor 12-BIT COP PRESCALER COP CLOCK COP MODULE 6-BIT COP COUNTER CLEAR COP COUNTER Figure 9-1. COP Block Diagram RESET CIRCUIT ...

Page 94

... An internal reset clears the COP prescaler and the COP counter. 9.3.6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev NOTE . During the break state, TST NOTE Figure 9-1. Freescale Semiconductor ...

Page 95

... Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor (CONFIG). (CONFIG). 6 ...

Page 96

... STOP instruction. When the STOP bit in the configuration register has the STOP instruction disabled, execution of a STOP instruction results in an illegal opcode reset. 9.8 COP Module During Break Mode The COP is disabled during a break interrupt when V MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev present on the RST pin. TST Freescale Semiconductor ...

Page 97

... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 10.2 CPU Registers Figure 10-1 shows the five CPU registers. CPU registers are not part of the memory map. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor 97 ...

Page 98

... NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 10-1. CPU Registers Unaffected by reset Figure 10-2. Accumulator ( Figure 10-3. Index Register (H: Bit 0 Bit Freescale Semiconductor ...

Page 99

... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Read: Write: Reset: MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor ...

Page 100

... The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 100 NOTE 2 1 Bit Freescale Semiconductor ...

Page 101

... Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Arithmetic/Logic Unit (ALU) 101 ...

Page 102

... IX1 SP1 9E67 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 Freescale Semiconductor ...

Page 103

... BRSET n,opr,rel Branch if Bit Set BSET n,opr Set Bit BSR rel Branch to Subroutine MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Description ← (PC rel ? ( – – – – – – REL PC ← (PC rel ? ( – ...

Page 104

... DIR INH 4A 1 INH 5A 1 – – – IX1 SP1 9E6A ff 5 INH 52 7 IMM DIR EXT IX2 – IX1 SP1 9EE8 ff 4 SP2 9ED8 Freescale Semiconductor ...

Page 105

... NEGA NEGX Negate (Two’s Complement) NEG opr,X NEG ,X NEG opr,SP NOP No Operation NSA Nibble Swap A MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Effect on CCR Description ← ( ← ( ← ( – – M ← ( ← ( ← ...

Page 106

... IX2 – IX1 SP1 9EE7 ff 4 SP2 9ED7 – DIR DIR EXT IX2 – IX1 SP1 9EEF ff 4 SP2 9EDF Freescale Semiconductor ...

Page 107

... Memory location N Negative bit 10.7 Opcode Map See Table 10-2. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Description ← (A) – (M) PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) – – 1 – – – INH SP ← ...

Page 108

Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...

Page 109

... A security feature prevents viewing of the FLASH contents security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor NOTE (1) 109 ...

Page 110

... Wait for a time, t (min. 10μs) nvs 5. Set the HVEN bit. 6. Wait for a time, t (min. 1ms) Erase 7. Clear the ERASE bit. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 110 HVEN Bit 0 MASS ERASE PGM Freescale Semiconductor ...

Page 111

... FLASH memory Only bytes which are currently $FF may be programmed. 1. When in Monitor mode, with security sequence failed see register instead of any FLASH address. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor NOTE (1) within the FLASH memory address range. NOTE ...

Page 112

... This applies particularly to $FFD4–$FFDF. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 112 NOTE NOTE NOTE maximum or t maximum. t PROG 32) NVH PGS PROG Characteristics. NOTE CAUTION is defined as the HV ≤ t maximum HV Freescale Semiconductor ...

Page 113

... PROG This row program algorithm assumes the row programmed are initially erased. Figure 11-2. FLASH Programming Flowchart MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor FLASH Program/Read Operation 1 Set PGM bit 2 Read the FLASH block protect register 3 Write any data to any FLASH address ...

Page 114

... These eight bits represent bits [13: 16-bit memory address. Bits [15:14] are 1s and bits [5:0] are 0s. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 114 NOTE NOTE BPR6 BPR5 BPR4 BPR3 the IRQ pin TST 2 1 Bit 0 BPR2 BPR1 BPR0 Freescale Semiconductor ...

Page 115

... FLASH, otherwise the operation will discontinue, and the FLASH will be on Standby Mode Standby Mode is the power saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH minimum. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor 16-bit memory address ...

Page 116

... Flash Memory MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 116 Freescale Semiconductor ...

Page 117

... The MODE bit in the INTSCR controls the triggering sensitivity of the IRQ pin. When an interrupt pin is edge-triggered only (MODE = 0), the interrupt remains set until a vector fetch, software clear, or reset occurs. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Figure 12-1 shows the 117 ...

Page 118

... Figure 12-1. IRQ Module Block Diagram Bit Unimplemented Figure 12-2. IRQ I/O Register Summary NOTE TO CPU FOR BIL/BIH INSTRUCTIONS IRQF SYNCHRO- IRQ NIZER INTERRUPT REQUEST HIGH TO MODE SELECT VOLTAGE DETECT LOGIC IRQF 0 IMASK ACK Freescale Semiconductor Bit 0 MODE 0 ...

Page 119

... To protect CPU interrupt flags during the break state, write the BCFE bit. With BCFE at 0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ interrupt flags. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor NOTE (BRK). IRQ Pin ...

Page 120

... This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 120 IRQF Bit 0 0 IMASK MODE ACK Freescale Semiconductor ...

Page 121

... A low level applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. KBD0 . TO PULLUP ENABLE . KB0IE . KBD3 TO PULLUP ENABLE KB3IE Figure 13-1. Keyboard Module Block Diagram MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor ACKK VDD RESET CLR KEYBOARD INTERRUPT FF MODEK INTERNAL BUS VECTOR FETCH DECODER KEYF ...

Page 122

... MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 122 Bit Unimplemented Figure 13-2. I/O Register Summary Bit 0 KEYF 0 IMASKK MODEK ACKK KBIE3 KBIE2 KBIE1 KBIE0 Freescale Semiconductor ...

Page 123

... The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor NOTE Keyboard Initialization 123 ...

Page 124

... Reset clears the IMASKK bit Keyboard interrupt requests masked 0 = Keyboard interrupt requests not masked MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 124 13.7.1 Keyboard Status and Control KEYF Unimplemented Register Bit 0 0 IMASKK MODEK ACKK Freescale Semiconductor ...

Page 125

... Each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. Reset clears the keyboard interrupt enable register PTAx pin enabled as keyboard interrupt pin 0 = PTAx pin not enabled as keyboard interrupt pin MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor ...

Page 126

... Keyboard Interrupt (KBI) MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 126 Freescale Semiconductor ...

Page 127

... V which will re-trigger the POR DD and reset the trip point to 3V operation. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor voltage falls below the LVI trip falling voltage voltage. Clearing the LVI reset disable bit, LVIRSTD, enables the LVI ...

Page 128

... This prevents a condition in which the MCU is TRIPR is approximately equal HYS , which causes the MCU to exit reset. LVISTOP FROM CONFIG LVI RESET level, software can monitor greater than TRIPF TRIPR Freescale Semiconductor Chapter Bit polling ...

Page 129

... If enabled in stop mode (LVISTOP bit in the configuration register is set), the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor NOTE [ V]) may be lower than this. (See ...

Page 130

... Low-Voltage Inhibit (LVI) MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 130 Freescale Semiconductor ...

Page 131

... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor , as long as vector addresses $FFFE TST ( reset vector is blank ($FFFE and $FFFF contain ...

Page 132

... Figure 15-1. Monitor Mode Circuit 68HC08 RST 0.1 μF (SEE NOTES 2 AND 3) IRQ V DDA V DDA CGMXFC 10 k OSC1 OSC2 PTA1 10 kΩ SSAD REFL V SSA DDAD REFH 0.1 μ kΩ PTA0 kΩ PTB0 PTB1 10 kΩ Freescale Semiconductor ...

Page 133

... IRQ), then the COP will be disabled. In the latter situation, after V can be removed from the IRQ pin in the interest of freeing the IRQ for normal functionality in monitor mode. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor applied on IRQ (condition set 1), the CGMOUT frequency is equal to TST NOTE ...

Page 134

... X 1 DNA IRQ = V TST 1 0 9600 External frequency always X 1 DNA divided 9600 PLL enabled (BCS set DNA monitor code Enters user mode — will X X — encounter an illegal address reset Enters X X — user mode Freescale Semiconductor ...

Page 135

... Pulling RST low will not exit monitor mode in this situation. Table 15-2 summarizes the differences between user mode and monitor mode. Modes User Monitor MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor POR RESET NO IS VECTOR NORMAL USER BLANK? YES MONITOR MODE ...

Page 136

... IRQ, then the divide by ratio is also set at 1024. If monitor mode DD and 23.7 3.0 V Control Timing Internal IRQ Frequency V 2.4576 MHz TST V 2.4576 MHz DD V 2.4576 MHz SS NEXT START BIT 7 STOP BIT BIT for this limit. Baud Rate (BPS) 9600 9600 9600 Freescale Semiconductor ...

Page 137

... FROM HOST WRITE WRITE ECHO Notes Echo delay, 2 bit times 2 = Cancel command delay, 11 bit times 3 = Wait 1 bit time before sending next byte. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor NOTE ADDRESS ADDRESS ADDRESS ADDRESS HIGH HIGH LOW LOW Figure 15-5 ...

Page 138

... MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 138 Table 15-4 Command Sequence ADDRESS ADDRESS ADDRESS ADDRESS HIGH HIGH LOW LOW Command Sequence ADDRESS ADDRESS ADDRESS ADDRESS HIGH HIGH LOW LOW Command Sequence FROM HOST IREAD IREAD DATA through Table 15-9. DATA RETURN DATA DATA DATA RETURN Freescale Semiconductor ...

Page 139

... READSP ECHO Table 15-9. RUN (Run User Program) Command Description Executes PULH and RTI instructions Operand None Data Returned None Opcode $28 MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Command Sequence FROM HOST DATA DATA IWRITE IWRITE ECHO Command Sequence FROM HOST ...

Page 140

... MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 140 SP HIGH BYTE OF INDEX REGISTER CONDITION CODE REGISTER ACCUMULATOR LOW BYTE OF INDEX REGISTER HIGH BYTE OF PROGRAM COUNTER LOW BYTE OF PROGRAM COUNTER NOTE Figure 15-8.) NOTE Freescale Semiconductor ...

Page 141

... Notes Echo delay, approximately 2 bit times 2 = Data return delay, approximately 2 bit times 4 = Wait 1 bit time before sending next byte 5 = Wait until the monitor ROM runs MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor FROM MCU Figure 15-8. Monitor Mode Entry Timing ...

Page 142

... Monitor ROM (MON) MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 142 Freescale Semiconductor ...

Page 143

... Port C Data Register $0002 Write: (PTC) Reset: Read: Port D Data Register $0003 Write: (PTD) Reset: Read: Data Direction Register A $0004 Write: (DDRA) Reset: MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor NOTE Bit PTB5 PTD6 PTD5 0 ...

Page 144

... Bit 0 DDRB3 DDRB2 DDRB1 DDRB0 DDRC1 DDRC0 DDRD3 DDRD2 DDRD1 DDRD0 PTE1 PTE0 0 0 DDRE1 DDRE0 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 PTCPUE1 PTCPUE0 Freescale Semiconductor ...

Page 145

... C — — — — — MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor DDR Module Control DDRA0 KBIE0 DDRA1 KBIE1 DDRA2 KBIE2 DDRA3 KBIE3 KBD — — — — — — — — DDRB0 ...

Page 146

... Unaffected by reset = Unimplemented Figure 16-2. Port A Data Register (PTA) Chapter 13 Keyboard Interrupt DDRA3 NOTE Bit 0 PTA3 PTA2 PTA1 PTA0 KBD3 KBD2 KBD1 KBD0 (KBI Bit 0 DDRA2 DDRA1 DDRA0 Freescale Semiconductor ...

Page 147

... A pins. Each bit is individually configurable and requires that the data direction register, DDRA, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit’s DDRA is configured for output mode. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor DDRAx RESET PTAx Figure 16-4 ...

Page 148

... PTAPUE3 PTB5 PTB4 Unaffected by reset AD5 AD4 = Unimplemented Figure 16-6. Port B Data Register (PTB) NOTE 2 1 Bit 0 PTAPUE2 PTAPUE1 PTAPUE0 Bit 0 PTB3 PTB2 PTB1 PTB0 AD3 AD2 AD1 AD0 Freescale Semiconductor ...

Page 149

... When bit DDRBx reading address $0001 reads the PTBx data latch. When bit DDRBx reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor ...

Page 150

... Unaffected by reset Figure 16-9. Port C Data Register (PTC) NOTE Accesses to PTB Read Write (3) Pin PTB5–PTB0 PTB5–PTB0 PTB5–PTB0 2 1 Bit 0 0 PTC1 PTC0 2 1 Bit 0 0 DDRC1 DDRC0 Freescale Semiconductor ...

Page 151

... Notes Don’t care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input. 4. I/O pin pulled internal pullup device. DD MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor NOTE NOTE DDRCx RESET PTCx Figure 16-11. Port C I/O Circuit Table 16-4 summarizes the operation of the port C pins. ...

Page 152

... MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 152 PTD6 PTD5 PTD4 PTD3 Unaffected by reset T2CH0 T1CH1 T1CH0 SPSCK = Unimplemented Chapter 22 Timer Interface Module 2 1 Bit 0 0 PTCPUE1 PTCPUE0 Bit 0 PTD2 PTD1 PTD0 MOSI MISO SS (TIM). Freescale Semiconductor ...

Page 153

... D pins as inputs Corresponding port D pin configured as output 0 = Corresponding port D pin configured as input Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Chapter 22 Timer Interface Module Table 16- ...

Page 154

... Table 16-5. Port D Pin Functions Accesses to DDRD I/O Pin Mode Read/Write (4) (1) DDRD6–DDRD0 Input (2) X DDRD6–DDRD0 Input, Hi-Z X Output DDRD6–DDRD0 V DD PTDPUEx INTERNAL PULLUP DEVICE PTDx Accesses to PTD Read Write Pin PTD6–PTD0 Pin PTD6–PTD0 PTD6–PTD0 PTD6–PTD0 Freescale Semiconductor (3) (3) ...

Page 155

... Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the SCI module. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. See MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor ...

Page 156

... READ DDRE ($000C) WRITE DDRE ($000C) WRITE PTE ($0008) READ PTE ($0008) MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 156 (SCI). (SCI NOTE DDREx RESET PTEx Figure 16-19. Port E I/O Circuit 2 1 Bit 0 0 DDRE1 DDRE0 PTEx Freescale Semiconductor ...

Page 157

... X Notes Don’t care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Table 16-6 summarizes the operation of the port E pins. Table 16-6. Port E Pin Functions Accesses to DDRE Read/Write (2) DDRE1–DDRE0 Output DDRE1– ...

Page 158

... Input/Output Ports (I/O) MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 158 Freescale Semiconductor ...

Page 159

... During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor NOTE NOTE NOTE 159 ...

Page 160

... Random-Access Memory (RAM) MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 160 Freescale Semiconductor ...

Page 161

... Noise error – Framing error – Parity error • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection • Configuration register bit, SCIBDSRC, to allow selection of baud rate clock source MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor 161 ...

Page 162

... The baud rate clock source for the SCI can be selected via the configuration bit, SCIBDSRC, of the CONFIG2 register ($001E). MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 162 Table 18-1 Table 18-1. Pin Name Conventions RxD PE1/RxD shows the full names and the generic TxD PE0/TxD Freescale Semiconductor ...

Page 163

... CONTROL SCIBDSRC FROM ENSCI CONFIG SL PRE- CGMXCLK A ÷ SCALER B IT12 => => MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor INTERNAL BUS LOOPS RECEIVE FLAG CONTROL CONTROL BKF RPF BAUD DIVIDER DATA SELECTION ∏ ÷ 16 CONTROL Figure 18-1 ...

Page 164

... Unaffected by reset SCP0 R SCR2 SCR1 Unaffected Figure 18-3. PARITY NEXT BIT START STOP BIT 7 BIT BIT PARITY NEXT BIT START BIT BIT 7 BIT 8 STOP BIT Freescale Semiconductor Bit 0 PTY 0 SBK 0 PEIE RPF SCR0 0 ...

Page 165

... CGMXCLK IT12 => => PRE- ÷ 4 SCALER SCP1 SCP0 SCR1 SCR2 SCR0 MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor INTERNAL BUS BAUD ÷ 16 SCI DATA REGISTER DIVIDER SHIFT REGISTER TXINV M PEN PARITY GENERATION PTY ...

Page 166

... Clears the SCI data register (SCDR) • Clears the R8 bit in SCC3 • Sets the break flag bit (BKF) in SCS2 • May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 166 Freescale Semiconductor ...

Page 167

... SCDR are empty and that no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests. 18.4.3 Receiver Figure 18-5 shows the structure of the SCI receiver. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor NOTE 1. Functional Description 167 ...

Page 168

... WAKEUP LOGIC PARITY CHECKING IDLE ILIE DMARE SCRF SCRIE DMARE SCRF SCRIE DMARE OR ORIE NF NEIE FE FEIE PE PEIE SCI DATA REGISTER 11-BIT RECEIVE SHIFT REGISTER RWU SCRF IDLE R8 ILIE SCRIE DMARE OR ORIE NF NEIE FE FEIE PE PEIE Freescale Semiconductor ...

Page 169

... Table 18-2 summarizes the results of the start bit verification samples. RT3, RT5, and RT7 Samples 000 001 010 011 100 MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor 18-6): START BIT START BIT START BIT QUALIFICATION VERIFICATION SAMPLING Figure 18-6. Receiver Data Sampling Table 18-2. Start Bit Verification ...

Page 170

... Table 18-3. Data Bit Recovery Data Bit Determination NOTE Table 18-4. Stop Bit Recovery Framing Error Flag Noise Flag Noise Flag Table 18-4 Noise Flag Freescale Semiconductor ...

Page 171

... RT cycles + 3 RT cycles = 163 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor MSB STOP DATA SAMPLES Figure 18-7 ...

Page 172

... IDLE OR NEXT CHARACTER DATA SAMPLES Figure 18-8. Fast Data Figure 18-8, the receiver counts 154 RT cycles at the point when · 154 160 – × 100 = 3.90% ------------------------- - 154 Figure 18-8, the receiver counts 170 RT cycles at the point when 170 176 – × 100 = 3.53% ------------------------- - 170 Freescale Semiconductor ...

Page 173

... Parity error (PE) — The PE bit in SCS1 is set when the SCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt requests. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor NOTE Functional Description 173 ...

Page 174

... The PE2/TxD pin is the serial data output from the SCI transmitter. The SCI shares the PE2/TxD pin with port E. When the SCI is enabled, the PE2/TxD pin is an output regardless of the state of the DDRE0 bit in data direction register E (DDRE). MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 174 for information on exiting wait mode. for information on exiting stop mode. Freescale Semiconductor ...

Page 175

... SCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver must be enabled to use loop mode. Reset clears the LOOPS bit Loop mode enabled 0 = Normal operation enabled MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor ...

Page 176

... Odd parity 0 = Even parity Changing the PTY bit in the middle of a transmission or reception can generate a parity error. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 176 NOTE Table 18-5. When enabled, the parity function Figure 18-3. Reset clears the PEN bit. NOTE Table 18-5. The Freescale Semiconductor ...

Page 177

... This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests. Reset clears the SCRIE bit SCRF enabled to generate CPU interrupt 0 = SCRF not enabled to generate CPU interrupt MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Table 18-5. Character Format Selection Character Format Start Bits Data Bits ...

Page 178

... No break characters being transmitted Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling SBK before the preamble begins causes the SCI to send a break character instead of a preamble. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 178 NOTE NOTE NOTE Freescale Semiconductor ...

Page 179

... This read/write bit enables SCI error CPU interrupt requests generated by the parity error bit, PE. See 18.8.4 SCI Status Register 1. Reset clears PEIE SCI error CPU interrupt requests from PE bit enabled 0 = SCI error CPU interrupt requests from PE bit disabled MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor ...

Page 180

... SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading SCS1 with SCRF set and then reading the SCDR. Reset clears SCRF Received data available in SCDR 0 = Data not available in SCDR MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 180 SCRF IDLE Bit Freescale Semiconductor ...

Page 181

... PE CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with PE set and then reading the SCDR. Reset clears the PE bit Parity error detected parity error detected MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor I/O Registers 181 ...

Page 182

... READ SCS1 SCRF = READ SCDR BYTE 1 Figure 18-13. Flag Clearing Sequence BYTE 4 READ SCS1 SCRF = READ SCDR BYTE 3 BYTE 4 READ SCS1 SCRF = READ SCDR BYTE Bit 0 0 BKF RPF Freescale Semiconductor ...

Page 183

... The baud rate register (SCBR) selects the baud rate for both the receiver and the transmitter. Address: $0019 Bit 7 Read: 0 Write: Reset Unimplemented Figure 18-16. SCI Baud Rate Register (SCBR) MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor ...

Page 184

... Table 18-7. SCI Baud Rate Selection Baud Rate Divisor (BD) 000 001 010 011 100 101 110 111 f BUS baud rate = ----------------------------------- - × × BUS baud rate = ----------------------------------- - × × Table 18-6. Reset clears SCP1 Table 18-7. Reset clears 128 Freescale Semiconductor ...

Page 185

... MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor SCR2, SCR1, Baud Rate and SCR0 Divisor (BD) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 000 1 001 2 010 4 011 ...

Page 186

... Serial Communications Interface (SCI) MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 186 Freescale Semiconductor ...

Page 187

... CGMOUT IAB IDB PORRST IRST R/W MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Figure Table 19-1. Signal Name Conventions Description Buffered version of OSC1 from clock generator module (CGM) PLL output PLL-based or OSC1-based clock output from CGM module (Bus clock = CGMOUT divided by two) ...

Page 188

... LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) INTERRUPT SOURCES CPU INTERFACE SBSW NOTE ILOP ILAD MODRST LVI Freescale Semiconductor Bit ...

Page 189

... CGMOUT, as shown in come from either an external oscillator or from the on-chip PLL. See OSC2 OSCILLATOR (OSC) OSC1 OSCSTOPENB FROM CONFIG CGMRCLK PHASE-LOCKED LOOP (PLL) MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Bit IF6 IF5 IF4 IF3 R R ...

Page 190

... CGMXCLK cycles, assuming that neither the POR nor the LVI was the source of the reset. See Table 19-2 for details. Figure 19-4 MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 190 19.6.2 Stop Mode. 19.4 SIM Counter), but an external reset does not. Each of shows the relative timing. 19.7 SIM Registers. Freescale Semiconductor ...

Page 191

... POR/LVI All others The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Figure 19-4. External Reset Timing Figure 19-5. An internal reset can be caused by an NOTE ...

Page 192

... RST or the IRQ pin. This prevents the COP from becoming disabled as a result of external noise. During a break state, V tst MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 192 32 32 CYCLES CYCLES Figure 19-7. POR Recovery on the RST pin disables the COP module. $FFFE $FFFF while the MCU is in monitor mode. tst Freescale Semiconductor ...

Page 193

... CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using crystals with the OSCSTOPENB bit set. External crystal applications should use the full stop recovery time, that is, with SSREC cleared. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor SIM Counter voltage falls to the DD 15 ...

Page 194

... Interrupt Entry Timing SP – – – CCR – 1 [7:0] Figure 19-9. Interrupt Recovery Timing for details.) The SIM counter is for counter control and Figure 19-8 shows VECT H VECT L START ADDR CCR V DATA H V DATA L OPCODE – 1 [15:8] OPCODE OPERAND Freescale Semiconductor ...

Page 195

... YES AS MANY INTERRUPTS AS EXIST ON CHIP MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor FROM RESET BREAK I BIT SET? YES INTERRUPT BIT SET? NO IRQ YES INTERRUPT? NO STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? ...

Page 196

... A software interrupt pushes PC onto the stack. A software interrupt does not push PC – hardware interrupt does. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 196 CLI LDA #$FF PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI . Interrupt Recognition Example NOTE NOTE BACKGROUND ROUTINE Freescale Semiconductor ...

Page 197

... These flags indicate the presence of interrupt requests from the sources shown Interrupt request present interrupt request present Bit 0 and Bit 1 — Always read 0 MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor Table 19-3. Interrupt Sources Interrupt Source Reset SWI instruction ...

Page 198

... Reserved Reserved 2 1 Bit 0 IF9 IF8 Table 19- Bit 0 0 I16 I15 Table 19-3. (TIM). The SIM puts the CPU into the Freescale Semiconductor ...

Page 199

... IAB WAIT ADDR IDB R/W Note: Previous data can be operand data or the WAIT opcode, depending on the last instruction. MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor WAIT ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 19-15. Wait Mode Entry Timing Low-Power Modes Figure 19-15 SAME ...

Page 200

... To minimize stop current, all pins configured as inputs should be driven MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 200 show the timing for WAIT recovery. $6E0B $6E0C $00FF $A6 $A6 $01 $ CYCLES CYCLES $A6 NOTE Figure 19-18 NOTE $00FE $00FD $00FC $6E RST VCT H RST VCT L shows stop mode entry timing. Freescale Semiconductor ...