CY7C1393CV18-250BZXC Cypress Semiconductor Corp, CY7C1393CV18-250BZXC Datasheet - Page 7

• Manufacturer Part Number: CY7C1393CV18-250BZXC
• Description: IC SRAM 18MBIT 250MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1393CV18-250BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 18M (1M x 18)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Definitions
Document #: 001-07162 Rev. *C
CQ
CQ
ZQ
DOFF
TDO
TCK
TDI
TMS
NC
NC/36M
NC/72M
NC/144M
NC/288M
V
V
V
V
Pin Name
REF
DD
SS
DDQ
Power Supply Power supply inputs to the core of the device.
Power Supply Power supply inputs for the outputs of the device.
Echo Clock
Echo Clock
Reference
Ground
Output
Input-
Input
Input
Input
Input
Input
N/A
N/A
N/A
N/A
N/A
IO
(continued)
CQ is referenced with respect to C. This is a free-running clock and is synchronized to the input clock
for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks is shown in the
CQ is referenced with respect to C. This is a free-running clock and is synchronized to the input clock
for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks is shown in the
Output impedance matching input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q
connected between ZQ and ground. Alternatively, this pin can be connected directly to V
enables the minimum impedance mode. This pin cannot be connected directly to GND or left uncon-
nected.
DLL turn off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing
in the DLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
can be connected to a pull up through a 10-Kohm or less pull up resistor. The device behaves in DDR-I
mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167
MHz with DDR-I timing.
TDO for JTAG.
TCK pin for JTAG.
TDI pin for JTAG.
TMS pin for JTAG.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Reference Voltage input. Static input used to set the reference level for HSTL inputs, Outputs, and AC
measurement points.
Ground for the device.
[x:0]
Switching Characteristics
Switching Characteristics
output impedance are set to 0.2 x RQ, where RQ is a resistor
Pin Description
CY7C1392CV18, CY7C1992CV18
CY7C1393CV18, CY7C1394CV18
on page 23.
on page 23.
DDQ
Page 7 of 30
, which
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