CY62158EV30LL-45ZSXI Cypress Semiconductor Corp, CY62158EV30LL-45ZSXI Datasheet - Page 9

• Manufacturer Part Number: CY62158EV30LL-45ZSXI
• Description: IC SRAM 8MBIT 45NS 44TSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY62158EV30LL-45ZSXI

• Memory Size: 8M (1M x 8)
• Package / Case: 44-TSOP II
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 45 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.2 V
• Maximum Operating Current: 25 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 2.5 V, 3.3 V
• Memory Configuration: 1M X 8
• Supply Voltage Range: 2.2V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Density: 8Mb
• Access Time (max): 45ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Address Bus: 20b
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Supply Current: 25mA
• Operating Supply Voltage (min): 2.2V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Word Size: 8b
• Number Of Words: 1M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2081; CY62158EV30LL-45ZSXI

Switching Waveforms
Write Cycle No. 1 (WE Controlled)
Write Cycle No. 2 (CE
Notes
Document #: 38-05578 Rev. *G
20. The internal write time of the memory is defined by the overlap of WE, CE
21. Data I/O is high impedance if OE = V
22. If CE
23. During this period, the I/Os are in output state. Do not apply input signals.
ADDRESS
ADDRESS
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
DATA I/O
DATA I/O
1
goes HIGH or CE
CE
CE
CE
CE
WE
WE
OE
OE
1
2
1
2
NOTE 23
2
goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
1
or CE
(continued)
IH
t
.
SA
2
t
HZOE
Controlled)
t
SA
[20, 21, 22]
[20, 21, 22]
t
t
AW
AW
t
SCE
t
WC
1
t
= V
WC
t
IL
PWE
, and CE
VALID DATA
t
t
PWE
SD
VALID DATA
t
2
SCE
t
= V
SD
IH
. All signals must be ACTIVE to initiate a write and any of these
t
HD
t
t
CY62158EV30 MoBL
HA
HA
t
HD
Page 9 of 16
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