CY62158EV30LL-45ZSXI Cypress Semiconductor Corp, CY62158EV30LL-45ZSXI Datasheet - Page 7

• Manufacturer Part Number: CY62158EV30LL-45ZSXI
• Description: IC SRAM 8MBIT 45NS 44TSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY62158EV30LL-45ZSXI

• Memory Size: 8M (1M x 8)
• Package / Case: 44-TSOP II
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 45 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.2 V
• Maximum Operating Current: 25 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 2.5 V, 3.3 V
• Memory Configuration: 1M X 8
• Supply Voltage Range: 2.2V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Density: 8Mb
• Access Time (max): 45ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Address Bus: 20b
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Supply Current: 25mA
• Operating Supply Voltage (min): 2.2V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Word Size: 8b
• Number Of Words: 1M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2081; CY62158EV30LL-45ZSXI

Switching Characteristics
Over the Operating Range
Document #: 38-05578 Rev. *G
Notes
Parameter
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1V/ns), timing reference levels of V
14. At any given temperature and voltage condition, t
15. t
16. The internal write time of the memory is defined by the overlap of WE, CE
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
levels of 0 to V
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
HZOE
, t
HZCE
[13]
[16]
, and t
CC(typ)
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE
CE
CE
CE
Write Cycle Time
CE
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High Z
WE HIGH to Low Z
HZWE
1
1
1
1
1
1
, and output loading of the specified I
LOW and CE
LOW and CE
HIGH or CE
LOW and CE
HIGH or CE
LOW and CE
transitions are measured when the outputs enter a high impedance state.
2
2
2
2
2
2
LOW to High Z
LOW to Power Down
[14]
[14, 15]
[14]
[14, 15]
HIGH to Data Valid
HIGH to Low Z
HIGH to Power Up
HIGH to Write End
HZCE
is less than t
[14, 15]
OL
[14]
/I
Description
OH
as shown in
LZCE
, t
HZOE
1
= V
AC Test Loads and Waveforms on page
IL
is less than t
, and CE
2
= V
LZOE
IH
. All signals must be ACTIVE to initiate a write and any of these
, and t
HZWE
is less than t
CY62158EV30 MoBL
5.
LZWE
for any given device.
Min
45
10
10
45
35
35
35
25
10
–
–
–
5
–
–
0
–
0
0
0
–
45 ns
CC(typ)
Max
45
45
22
18
18
45
18
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 7 of 16
/2, input pulse
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
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