C8051F545-IQR Silicon Labs, C8051F545-IQR Datasheet - Page 195
![no-image](/images/no-image-200.jpg)
C8051F545-IQR
Manufacturer Part Number
C8051F545-IQR
Description
8-bit Microcontrollers - MCU 50 MIPS 8 kB 1 kB SPI UART I2C
Manufacturer
Silicon Labs
Datasheet
1.C8051F546-IMR.pdf
(274 pages)
Specifications of C8051F545-IQR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F545-IQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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SFR Definition 20.2. SMB0CN: SMBus Control
SFR Address = 0xC0; Bit-Addressable; SFR Page =0x00
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
ARBLOST SMBus Arbitration Lost
TXMODE SMBus Transmit Mode
MASTER SMBus Master/Slave
ACKRQ
Name
MASTER
STO
ACK
STA
SI
R
7
0
Indicator. This read-only bit
indicates when the SMBus is
operating as a master.
Indicator. This read-only bit
indicates when the SMBus is
operating as a transmitter.
SMBus Start Flag.
SMBus Stop Flag.
SMBus Acknowledge
Request.
Indicator.
SMBus Acknowledge.
SMBus Interrupt Flag.
This bit is set by hardware
under the conditions listed in
Table 15.3. SI must be cleared
by software. While SI is set,
SCL is held low and the
SMBus is stalled.
TXMODE
R
6
0
Description
R/W
STA
5
0
STO
R/W
Rev. 1.1
0: SMBus operating in
slave mode.
1: SMBus operating in
master mode.
0: SMBus in Receiver
Mode.
1: SMBus in Transmitter
Mode.
0: No Start or repeated
Start detected.
1: Start or repeated Start
detected.
0: No Stop condition
detected.
1: Stop condition detected
(if in Slave Mode) or pend-
ing (if in Master Mode).
0: No Ack requested
1: ACK requested
0: No arbitration error.
1: Arbitration Lost
0: NACK received.
1: ACK received.
0: No interrupt pending
1
4
0
:
Interrupt Pending
ACKRQ
Read
R
3
0
ARBLOST
R
2
0
N/A
N/A
0: No Start generated.
1: When Configured as a
Master, initiates a START
or repeated START.
0: No STOP condition is
transmitted.
1: When configured as a
Master, causes a STOP
condition to be transmit-
ted after the next ACK
cycle.
Cleared by Hardware.
N/A
N/A
0: Send NACK
1: Send ACK
0: Clear interrupt, and initi-
ate next state machine
event.
1: Force interrupt.
C8051F54x
ACK
R/W
1
0
Write
R/W
SI
0
0
195
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