C8051F545-IQR Silicon Labs, C8051F545-IQR Datasheet - Page 181
C8051F545-IQR
Manufacturer Part Number
C8051F545-IQR
Description
8-bit Microcontrollers - MCU 50 MIPS 8 kB 1 kB SPI UART I2C
Manufacturer
Silicon Labs
Datasheet
1.C8051F546-IMR.pdf
(274 pages)
Specifications of C8051F545-IQR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
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Part Number:
C8051F545-IQR
Manufacturer:
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LIN Register Definition 19.5. LIN0CTRL: LIN0 Control Register
Indirect Address = 0x08
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
WUPREQ
RSTERR
RSTINT
STREQ
DTACK
SLEEP
Name
STOP
TXRX
STOP
W
7
0
Stop Communication Processing Bit. (slave mode only)
This bit always reads as 0.
0: No effect.
1: Block the processing of LIN communications until the next SYNC BREAK signal.
Sleep Mode Bit. (slave mode only)
0: Wake the device after receiving a Wakeup interrupt.
1: Put the device into sleep mode after receiving a Sleep Mode frame or a bus idle
timeout.
Transmit / Receive Selection Bit.
0: Current frame is a receive operation.
1: Current frame is a transmit operation.
Data Acknowledge Bit. (slave mode only)
Set to 1 after handling a data request interrupt to acknowledge the transfer. The bit
will automatically be cleared to 0 by the LIN controller.
Reset Interrupt Bit.
This bit always reads as 0.
0: No effect.
1: Reset the LININT bit (LIN0ST.3).
Reset Error Bit.
This bit always reads as 0.
0: No effect.
1: Reset the error bits in LIN0ST and LIN0ERR.
Wakeup Request Bit.
Set to 1 to terminate sleep mode by sending a wakeup signal. The bit will automati-
cally be cleared to 0 by the LIN controller.
Start Request Bit. (master mode only)
1: Start a LIN transmission. This should be set only after loading the identifier, data
length and data buffer if necessary.
The bit is reset to 0 upon transmission completion or error detection.
SLEEP
R/W
6
0
TXRX
R/W
5
0
DTACK
R/W
Rev. 1.1
4
0
Function
RSTINT
W
3
0
RSTERR
W
2
0
C8051F54x
WUPREQ
R/W
1
0
STREQ
R/W
0
0
181
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