MCIMX6U6AVM08AB Freescale Semiconductor, MCIMX6U6AVM08AB Datasheet
MCIMX6U6AVM08AB
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MCIMX6U6AVM08AB Summary of contents
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... Each processor provides a 32/64-bit DDR3/LVDDR3/LPDDR2-800 memory interface and a number of other interfaces for connecting peripherals, © 2012 Freescale Semiconductor, Inc. All rights reserved. Document Number: IMX6SDLAEC Rev. 1, 11/2012 MCIMX6SxAxxxxxB MCIMX6UxAxxxxxB Package Information Plastic Package BGA Case 2240 mm, 0 ...
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... The security features will be discussed in detail in the i.MX 6Solo/6DualLite Security Reference Manual (to be released soon). i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev ® ES 2.0 3D graphics accelerator with a shader and a 2D graphics 2 S serial audio, and PCIe-II). Freescale Semiconductor ...
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... The latest part numbers are available on the web page freescale.com/imx6series. If the desired part number is not listed in the web page freescale.com/imx6series or contact a Freescale representative. Solo/DualLite Part Number CPU MCIMX6U6AVM08AB i.MX 6DualLite With VPU, GPU, no EPD MCIMX6U4AVM08AB i.MX 6DualLite With GPU, no VPU, no EPD 800 MHz MCIMX6U1AVM08AB i.MX 6DualLite no GPU, no VPU, no display 800 MHz MCIMX6S6AVM08AB i ...
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... Extended Consumer: - 105C E Industrial: -40 to +105C C Automotive: - 125C Silicon Rev B Rev 1.1 B Fusing % Real Co dec o ff & no HDCP o r DTCP A Real Co dec o ff with HDCP on C Frequency $$ 2 800 MHz GHz 10 Package Type ROHS MAPBGA 21x21 0.8mm VM Freescale Semiconductor ...
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... One Parallel 24-bit display port 225 Mpixels/sec (for example, WUXGA dual HD1080 and WXGA at 60 Hz) — LVDS serial ports—One port up to 165 Mpixels/sec or two ports MP/sec (for example, WUXGA at 60 Hz) each — HDMI 1.4 port i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Introduction Table 9, "Operating Ranges," on page 5 ...
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... The theoretical maximum performance of 1 Gbps ENET is limited to 470 Mbps (total for Tx and Rx) due to internal bus throughput limitations. The actual measured performance in optimized environment 400 Mbps. For details, see the ERR004512 erratum in the i.MX 6Solo/6DualLite errata document (IMX6SDLCE). i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev Mbps Freescale Semiconductor ...
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... The actual feature set depends on the part numbers as described in "Orderable Part Numbers," on page acceleration, and 2D and 3D hardware graphics acceleration may not be enabled for specific part numbers. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor NOTE 3. Functions, such as video hardware Introduction Table 1, ...
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... MIPI HDMI 1.4 Display Display HDMI DSI/MIPI MMC/SD AP Peripherals eMMC/eSD uSDHC (4) MMC/SD SDXC AUDMUX 2 I C(4) PWM (4) Modem IC OCTP_CTRL IOMUXC KPP GPIO Keypad CAN(2) 1-Gbps ENET MLB 150 DTCP HSI/MIPI Ethernet 10/100/1000 USB OTG + Mbps 3 HS Ports MLB/Most Network Freescale Semiconductor ...
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... Binary-BCH ECC Processor CAAM Cryptographic accelerator and assurance module i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor NOTE Table 2. i.MX 6Solo/6DualLite Modules List Subsystem ARM The ARM Core Platform includes 1x (Solo) Cortex-A9 core for i.MX 6Solo and 2x (Dual) Cortex-A9 cores for i.MX 6DualLite. It also includes associated sub-blocks, ...
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... Provides encryption function according to Digital Peripherals Transmission Content Protection standard for traffic over MLB150. Connectivity Full-duplex enhanced Synchronous Serial Interface, Peripherals with data rate Mbit/ configurable to support Master/Slave modes, four chip selects to support multiple peripherals. Brief Description Freescale Semiconductor ...
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... Enhanced Periodic EPIT-2 Interrupt Timer ESAI Enhanced Serial Audio Interface i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Subsystem Connectivity The Ethernet Media Access Controller (MAC) is Peripherals designed to support 10/100/1000 Mbps Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media ...
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... Electromagnetic interference (EMI) environment of a vehicle, cost-effectiveness and required bandwidth. The FlexCAN module is a full implementation of the CAN protocol specification, Version 2.0 B, which supports both standard and extended message frames. Freescale Semiconductor ...
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... C-4 i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Subsystem Security Electrical Fuse Array. Enables to setup Boot Modes, Security Levels, Security Keys, and many other system parameters. The i.MX 6Solo/6DualLite processors consist of 512x8-bit fuse fox accessible through OCOTP_CTRL interface. System Control Used for general purpose input/output to external ICs ...
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... The module is backward compatible to MLB-50. Connectivity DDR Controller has the following features: Peripherals • Supports 16/32-bit DDR3-800 (LV) or LPDDR2-800 in i.MX 6Solo • Supports 16/32/64-bit DDR3-800 (LV) or LPDDR2-800 in i.MX 6DualLite • Supports 2x32 LPDDR2-800 in i.MX 6DualLite • Supports GByte DDR memory space Brief Description ® Freescale Semiconductor ...
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... Boot ROM 96KB ROMCP ROM Controller with Patch i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Subsystem Security The On-Chip OTP controller (OCOTP_CTRL) provides an interface for reading, programming, and/or overriding identification and control information stored in on-chip fuse elements. The module supports electrically-programmable poly fuses (eFUSEs) ...
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... A standard audio file transfer format, developed jointly Peripherals by the Sony and Phillips corporations. Has Transmitter and Receiver functionality. Security Secure Non-Volatile Storage, including Secure Real Time Clock, Security State Machine, Master Key Control, and Violation/Tamper Detection and reporting. Brief Description Freescale Semiconductor ...
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... USBOH3 USB 2.0 High Speed OTG and 3x HS Hosts VDOA VDOA i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Subsystem Connectivity The SSI is a full-duplex synchronous interface, which is Peripherals used on the AP to provide connectivity with off-chip audio peripherals. The SSI supports a wide variety of ...
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... Support 16-bit (in muxed IO mode only) NOR-Flash memories, at slow frequency • Multiple chip selects Clocks, Resets, and The XTALOSC module enables connectivity to external Power Control crystal oscillator device typical application use-case used for 24 MHz oscillator to provide USB required frequency. Brief Description Freescale Semiconductor ...
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... If this clock is used as a reference for USB and PCIe, then there are strict frequency tolerance and jitter requirements. See OSC24M chapter and relevant interface specifications chapters for details. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Section 6, “Package Information and Contact Table 3. Special Signal Considerations ...
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... The user must either float this signal or tie it to GND. The impedance calibration process requires connection of reference resistor 200 Ω 1% precision PCIE_REXT resistor on PCIE_REXT pad to ground. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev Remarks Table 4. Use of external resistors is unnecessary. However, Freescale Semiconductor ...
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... RGMII_RXC, RGMII_TD0, RGMII_TD1, RGMII_TD2, RGMII_TD3, RGMII_TX_CTL, RGMII_TXC USB USB_H1_DN, USB_H1_DP, USB_H1_VBUS, USB_OTG_CHD_B, USB_OTG_DN, USB_OTG_DP, USB_OTG_VBUS 1 In this case, the BSR chain will not work. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Remarks Table 4. JTAG Controller Interface Summary I/O Type Input Input Input 3-state output ...
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... Supplies denoted as I/O supply VDD_SNVS_IN VDDHIGH_IN VBUS USB_DP/USB_DN out Table 6 for a quick reference Topic appears … on page 22 on page 23 on page 24 on page 26 on page 27 on page 29 on page 30 on page 30 Min Max Unit -0.3 1.5 V -0.3 1.3 V -0.5 3.6 V -0.4 1.975 V -0.3 2.8 V -0.3 2.8 V -0.3 3.3 V -0.3 3.6 V — 5.25 V -0.3 3. -0.5 OVDD +0.3 V Freescale Semiconductor ...
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... Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Symbol V esd T STORAGE Table 8 ...
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... Should be supplied from the same supply as VDDHIGH_IN if the system does not require keeping real time and other data on OFF state. LPDDR2, DDR3-U DDR3 DDR3_L 1.15 V – 1. HSIC 1.2 V mode 1.43 V – 1. RMGII 1.5 V mode 1.70 V – 1. RMGII 1.8 V mode 2.25 V – 2.625 V in RMGII 2.5 V mode Freescale Semiconductor ...
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... This supply also powers the pre-drivers of the DDR IO pins, hence, it must be always provided, even when LVDS is not used Table 10 shows on-chip LDO regulators that can supply on-chip loads. Table 10. On-Chip LDOs Voltage Source VDDHIGH_CAP i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 9. Operating Ranges (continued) 1 Min Typ Max Unit 1 ...
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... Automotive and Infotainment Applications Processors, Rev and their On-Chip Loads (continued) Load HDMI_VP Board-level connection to VDDSOC_CAP PCIE_VP PCIE_VPTX Table 11. External Input Clock Frequency Symbol Min f — 32.768 ckil f xtal Comment 2 3 Typ Max Unit 3 /32.0 — kHz 24 MHz Freescale Semiconductor ...
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... Power Line VDDARM_IN VDDSOC_IN VDDHIGH_IN VDD_SNVS_IN USB_OTG_VBUS/USB_H1_VBUS (LDO 3P0) i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 11 are required for use with Freescale BSPs to ensure precise time Table 12 represent a use case designed specifically to show the Table 12. Maximal Supply Currents Conditions ...
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... Use maximal IO equation N=24 Use maximal IO equation N=20 Use maximal IO equation N=53 Use maximal IO equation N=6 Use maximal IO equation N=12 Use maximal IO equation N=6 Use maximal IO equation N=6 Use maximal IO equation N=11 Use maximal IO equation N=26 Use maximal IO equation MISC — 1 Unit 4 — Freescale Semiconductor ...
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... XTAL and bandgap are disabled 1 The typical values shown here are for information only and are not guaranteed. These values are average values measured on a typical wafer at 25°C. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Test Conditions VDDARM_IN (1.4V) VDDSOC_IN (1.4V) VDDHIGH_IN (3.0V) Total VDDARM_IN (1 ...
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... Test Conditions Supply 5G Operations PCIE_VP (1.1 V) PCIE_VPTX (1.1 V) PCIE_VPH (2.5 V) 2.5G Operations PCIE_VP (1.1 V) PCIE_VPTX (1.1 V) PCIE_VPH (2 Operations PCIE_VP (1.1 V) PCIE_VPTX (1.1 V) PCIE_VPH (2.5 V) 2.5G Operations PCIE_VP (1.1 V) PCIE_VPTX (1.1 V) PCIE_VPH (2.5 V) PCIE_VP (1.1 V) PCIE_VPTX (1.1 V) PCIE_VPH (2.5 V) PCIE_VP (1.1 V) PCIE_VPTX (1.1 V) PCIE_VPH (2.5 V) NVCC_PLL_OUT (1.1 V) <0.5 μA Max Current Unit 2 2 2.4 12 1.3 mA 0.18 0.36 Freescale Semiconductor ...
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... If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other supply is switched on. • If VDDARM_IN and VDDSOC_IN are connected to different external supply sources, then the following restrictions apply: i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 16. HDMI PHY Current Drain Supply HDMI_VPH HDMI_VP HDMI_VPH ...
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... There are three digital LDO regulators (“Digital”, because of the logic loads that they drive, not because of their construction). The advantages of the regulators are to reduce the input supply variation because of i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev NOTE NOTE NOTE Section 6, “Package Information NOTE Freescale Semiconductor ...
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... Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed. Active-pull-down can also be enabled for systems requiring this feature. An alternate self-biased low-precision weak-regulator is included that can be i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Electrical Characteristics 33 ...
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... Table 18. 528 MHz PLL’s Electrical Parameters Parameter Clock output range Reference clock Lock time i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev Value 650 MHz ~1.3 GHz 24 MHz <11250 reference cycles Value 528 MHz PLL output 24 MHz <11250 reference cycles Freescale Semiconductor ...
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... Lock time 4.4.6 ARM PLL Parameter Clock output range Reference clock Lock time i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 21. MLB PLL’s Electrical Parameters Table 22. ARM PLL’s Electrical Parameters Electrical Characteristics Value 500 MHz 24 MHz <11250 reference cycles ...
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... RTC consumes. The ring oscillator consumes 1 μA when ring oscillator is inactive, 20 μA when the ring oscillator is running. Another 1.5 μA is drawn from vdd_rtc in the power_detect block. So, the total current is 6.5 μA on vdd_rtc when the ring oscillator is not running. Comments Freescale Semiconductor ...
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... MLB I/O The term ‘OVDD’ in this section refers to the associated supply rail of an input or output. Figure 3. Circuit for Parameters Voh and Vol for I/O Cells i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 23. OSC32K Main Characteristics Typ Max 14 MΩ ...
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... OVDD R_Keeper VI =.3*OVDD .7* OVDD are guaranteed per the Min Max Units OVDD- 0.15 V 0.7*OVD OVDD 0.3*OVD V D 250 mV 250 mV 0.5*OVD mV D 0.5*OVD mV D 212 100 105 175 kΩ Freescale Semiconductor ...
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... Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document. 2 The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Symbol Test Conditions VOH Ioh= -0.1mA VOL Iol= 0 ...
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... Vtt Vtt tracking OVDD/2 Rres Rkeep Iin VI = 0,VI = OVDD Table 9, unless otherwise Min Max Unit 1 0.8*OVDD V 0.2*OVDD V 0.8*OVDD V 0.2*OVDD V 0.49*ovdd 0.51*ovdd V 2 Vref +0.1 OVDD V OVSS Vref-0 0.2 See Note V 3 See Note -0.2 V 0.49*OVDD 0.51*OVDD V - Ω 10 105 165 kΩ μA -2.9 2.9 Freescale Semiconductor ...
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... LVDS I/O • MLB I/O The GPIO and DDR I/O load circuit and output transition time waveforms are shown in Figure 5. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 27. LVDS I/O DC Characteristics Symbol Test Conditions Rload-100 Ω Diff VOD VOH IOH = 0 mA VOL ...
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... Cload, fast slew rate tr Cload, slow slew rate 15 pF Cload, fast slew rate trm — OVDD 80% 20 Table 29 and Table 30, Min Typ Max Unit 2.72/2.79 — — 1.51/1.54 3.20/3.36 — — 1.96/2.07 ns 3.64/3.88 — — 2.27/2.53 4.32/4.50 — — 3.16/3.17 — — Freescale Semiconductor ...
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... Skew between pad rise/fall asymmetry + skew caused by SSN 1 Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Symbol Test Condition tr Cload, slow slew rate 15 pF Cload, fast slew rate ...
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... Relative to Vref Vpeak — Varea 400 MHz tsr Driver impedance = 34 Ω t clk = 400 MHz SKD Figure 1 Min Typ Max — OVDD 0 — Vref - 0.175 0.35 — — Vref - 0.15 — Vref + 0.15 — — 0.4 — — 0.5 2.5 — 5 — — 0.1 6. Freescale Semiconductor Unit V-ns V/ns ns ...
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... Signal/Data sampling flip-flop and Transmitter, Cycle 3 includes clock-to-output delay of Signal/Data clocked receiver, Cycle 4 includes clock-to-output delay of Signal/Data sampling flip-flop. MLB 6-pin pipeline diagram is shown in i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 33. I/O AC Parameters of LVDS Pad Symbol Test Condition t SKD Rload = 100 Ω ...
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... Table 34. I/O AC Parameters of MLB PHY Symbol Test Condition t SKD Rload = 50 Ω t between padp TLH t THL fclk_ext fclk_pll NOTE Min Typ Max — — 0.1 — — 1 and padn — — 1 — — — 102.4 — — — 307.2 Figure 9). Freescale Semiconductor Unit ns MHz MHz ...
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... U,(V) OVDD Vref1 Vref 0 Vovdd - Vref1 Rpu = Rpd = Vovdd - Vref2 Figure 9. Impedance Matching Load for Measurement i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor OVDD PMOS (Rpu) Ztl Ω inches pad NMOS (Rpd) OVSS Vref2 × Ztl Vref1 Vref2 × Ztl ...
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... Table 37. DDR I/O Output Buffer Impedance Test Conditions DSE(Drive NVCC_DRAM=1.5 V Strength) (DDR3) DDR_SEL=11 Typ Value Unit 260 130 90 Ω Typ Value Unit 150 75 50 Ω Typical Unit NVCC_DRAM=1.2 V (LPDDR2) DDR_SEL=10 Hi-Z Hi-Z 240 240 120 120 Freescale Semiconductor Ω ...
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... POR_B (Input) ID CC1 Duration of POR_B to be qualified as valid (input slope = 5 ns) i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Test Conditions Zo Table 39 lists the timing parameters. CC1 Figure 10. Reset Timing Diagram Table 39. Reset Timing Parameters ...
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... Table 40. WDOG_B Timing Parameters Parameter NOTE NOTE Table 41. EIM Signal Cross Reference Data Sheet Nomenclature, Reference Manual External Signals and Pin Multiplexing Chapter, and IOMUXC Controller Chapter Nomenclature EIM_BCLK EIM_CSx EIM_RW EIM_OE EIM_EBx Min Max Unit 1 — RTC_XTALI cycle Freescale Semiconductor ...
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... EIM_EB3 1 For more information on configuration ports mentioned in this table, see the i.MX 6Solo/6DualLite reference manual. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Data Sheet Nomenclature, Reference Manual External Signals and Pin Multiplexing Chapter, and IOMUXC Controller Chapter Nomenclature EIM_LBA EIM_A[25:16], EIM_DA[15:0] ...
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... EIM module. All EIM output control WE2 ... WE1 WE4 WE6 WE8 WE10 WE12 WE14 WE16 Figure 12. EIM Outputs Timing Diagram WE18 WE19 WE20 WE21 Figure 13. EIM Inputs Timing Diagram WE3 WE5 WE7 WE9 WE11 WE13 WE15 WE17 Freescale Semiconductor ...
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... Output Data Valid 1.25 WE17 Clock rise to 0 Output Data 1.25 Invalid WE18 Input Data setup 2 time to Clock rise i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 43. EIM Bus Timing Parameters BCD = 0 BCD = 1 Max Min Max — — 0 — ...
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... Min Max — 2 — — 4 — — 2 — WE4 Address v1 WE6 WE14 WE15 WE10 WE12 WE18 1 BCD = 2 BCD = 3 Min Max Min Max — — — — — — — — — — — — WE5 WE7 WE11 WE13 D(v1) WE19 Freescale Semiconductor ...
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... ADV_B OE_B BEy_B Figure 16. Muxed Address/Data (A/D) Mode, Synchronous Write Access, WSC=6,ADVA=0, ADVN=1, and In 32-bit muxed address/data (A/D) mode the 16 MSBs are driven on the data bus. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor WE4 Address V1 WE6 WE8 WE14 WE15 WE12 ...
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... Manual (IMX6SDLRM) for the EIM programming model. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev WE4 WE5 Address V1 WE6 WE15 WE10 WE12 Table 44 help you determine timing parameters relative to the chip WE19 Data WE18 WE7 WE11 WE13 Figure 18 through Freescale Semiconductor ...
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... Figure 18. Asynchronous Memory Read Access (RWSC = 5) INT_CLK MAXCSO CSx_B ADDR/ M_DATA WE_B ADV_B OE_B BEy_B MAXCO Figure 19. Asynchronous A/D Muxed Read Access (RWSC = 5) i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor start of access WE31 Address V1 WE39 WE35 WE37 D(V1) WE43 MAXDI start of access ...
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... BEy_B Figure 21. Asynchronous A/D Muxed Write Access i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev WE31 Address V1 WE33 WE39 WE45 D(V1) WE41 WE31 D(V1) Addr. V1 WE32A WE33 WE40A WE39 WE45 WE32 Next Address WE34 WE40 WE46 WE42 WE41 WE42 WE34 WE46 WE42 Freescale Semiconductor ...
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... OE_B BEy_B DATA[7:0] DTACK CSx_B ADDR Last Valid Address WE_B ADV_B OE_B BEy_B DATA DTACK i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor WE31 Address V1 WE39 WE35 WE37 D(V1) WE43 WE47 Figure 22. DTACK Read Access (DAP=0) WE31 Address V1 WE33 WE39 WE45 ...
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... RCSN) — (RBEA - RCSA) — (RBEN- RCSN) — (ADVA - CSA) — CSN 3 + (ADVN + ADVA + 1 - CSA) — WCSA — (WADVN + WADVA + ADH + 1 - WCSA) — CSN — — — — — — Freescale Semiconductor ...
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... In this table, ADVN means WADVN when write operation or RADVN when read operation this table, ADVA means WADVA when write operation or RADVA when read operation. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Determination by Synchronous measured 1 parameters MAXCO - MAXCSO + MAXDI ...
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... Automotive and Infotainment Applications Processors, Rev DDR4 DDR5 DDR4 DDR5 DDR4 DDR7 COL/BA Symbol Table DDR1 DDR2 CK = 400 MHz Unit Min Max 0.47 0. 0.47 0. 800 — ps 580 — ps 800 — ps 580 — ps Freescale Semiconductor 45. ...
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... To receive the reported setup and hold values, write calibration should be performed in order to locate the DQS in the middle of DQ window. 2 All measurements are in reference to Vref level. 3 Measurements were done using balanced load and 25 Ω resistor from outputs to VDD_REF. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor DDR22 DDR23 DDR18 DDR17 Data Data ...
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... Measurements were done using balanced load and 25 Ω resistor from outputs to VDD_REF. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev DATA DATA DATA DATA DDR26 Figure 26. DDR3/DDR3L Read Cycle Table 47. DDR3/DDR3L Read Cycle Parameter DATA DATA DATA DATA CK = 400 MHz Symbol Min Max — 450 — Freescale Semiconductor Unit ps ...
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... LP6 CKE hold time 1 All measurements are in reference to Vref level. 2 Measurements were done using balanced load and 25 Ω resistor from outputs to VDD_REF. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor LP4 LP6 LP3 LP3 LP4 LP4 Table 48. LPDDR2 Timing Parameter ...
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... LP17 LP18 Figure 28. LPDDR2 Write Cycle Table 49. LPDDR2 Write Cycle Parameter Table LP18 Data Data Data Data LP18 CK = 400 MHz Symbol Min Max t 375 — 375 — -0.25 +0.25 DQSS t 0.4 - DQSH t 0.4 - DQSL Freescale Semiconductor 49. Unit ps ps tCK tCK tCK ...
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... GPMI signals at the module level for different operations under asynchronous mode. Table 51 describes the timing parameters (NF1–NF17) that are shown in the figures. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor DATA DATA DATA DATA LP26 Figure 29 ...
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... Figure 30. Command Latch Cycle Timing Diagram CLE CEn WE ALE IO[7:0] Figure 31. Address Latch Cycle Timing Diagram i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev NF2 NF1 NF3 NF5 NF6 NF7 NF8 NF9 Command NF1 NF3 NF4 NF10 NF11 NF5 NF7 NF6 NF8 NF9 Address NF4 Freescale Semiconductor ...
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... Table 51. Asynchronous Mode Timing Parameters ID Parameter NF1 CLE setup time NF2 CLE hold time NF3 CEn setup time NF4 CE hold time i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor NF1 NF3 NF10 NF11 NF5 NF6 NF8 NF9 Data to NF NF14 NF15 ...
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... tDSR N/A tDHR N/A 1 (continued) Example Timing for ≈ 100 GPMI Clock MHz Unit Min. Max — — — — — — — — — — ns (Figure 32). Freescale Semiconductor ...
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... CE_N CLE ALE CLK W/R# DQS DQS output enable DQ[7:0] DQ[7:0] Output enable Figure 34. Source Synchronous Mode Command and Address Timing Diagram i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor NF20 NF21 NF20 CMD ADD NF23 Electrical Characteristics NF19 NF21 NF22 ADD NF24 71 ...
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... Electrical Characteristics NF18 CE_N CLE ALE CLK W/R# DQS DQS output enable DQ[7:0] DQ[7:0] Output enable Figure 35. Source Synchronous Mode Data Write Timing Diagram i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev NF25 NF23 NF25 NF22 NF27 NF27 NF19 NF26 NF24 NF27 Freescale Semiconductor ...
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... W/R# DQS DQS output enable DQ[7:0] DQ[7:0] Output enable Figure 36. Source Synchronous Mode Data Read Timing Diagram DQS DQ[7:0] i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor NF25 NF22 tDVW D0 D1 tDQSQ tQHS Figure 37. DQS/DQ Read Valid Window Electrical Characteristics NF19 NF26 NF24 NF25 ...
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... PRE_DELAY x tCK tPOST POST_DELAY x tCK tCALS 0.5 x tCK tCALH 0.5 x tCK tDQSS tCK Figure 37 shows the timing diagram of DQS/DQ read valid NOTE Section 4.10.1, “Asynchronous for details. 1 Timing Unit Max. — ns — ns — ns — — ns — ns — ns — ns — ns Freescale Semiconductor ...
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... Read and Write Timing Figure 38. Samsung Toggle Mode Data Write Timing i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Electrical Characteristics 75 ...
Page 76
... NF21 Command/address DQ hold time NF22 clock period i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev Timing T = GPMI Clock Cycle Symbol Min. tCE CE_DELAY x tCK tCH 0.5 x tCK tCAS 0.5 x tCK tCAH 0.5 x tCK tCK 7.5 Unit Max. — ns — ns — ns — Freescale Semiconductor ...
Page 77
... ECSPI Timing Parameters This section describes the timing parameters of the ECSPI blocks. The ECSPI have separate timing parameters for master and slave modes. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor T = GPMI Clock Cycle Symbol Min. tPRE (PRE_DELAY+1) x tCK ...
Page 78
... Hmiso t SDRY lists the ECSPI master mode timing CS5 CS6 CS4 Min Max 43 — 15 21.5 — 7 — — Half SCLK period — Half SCLK period - 4 — Half SCLK period - 2 — — 0 — 5 — Freescale Semiconductor Unit ...
Page 79
... SSx Lead Time (CS setup time) CS6 SSx Lag Time (CS hold time) CS7 MOSI Setup Time CS8 MOSI Hold Time CS9 MISO Propagation Delay (C i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 55 lists the ECSPI slave mode timing CS2 CS2 Symbol t clk t SW ...
Page 80
... Freescale Semiconductor 3 Unit ...
Page 81
... Periodically sampled and not 100% tested. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 1,2 Symbol Expression 5 — ...
Page 82
... Electrical Characteristics 63 SCKT (Input/Output) FST (Bit) Out FST (Word) Out Data Out FST (Bit) In FST (Word) In i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev First Bit Figure 42. ESAI Transmitter Timing 83 87 Last Bit 91 Freescale Semiconductor ...
Page 83
... SCKR (Input/Output) FSR (Bit) Out FSR (Word) Out Data In FSR (Bit) In FSR (Word) In i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor First Bit Figure 43. ESAI Receiver Timing Electrical Characteristics 70 72 Last Bit 75 83 ...
Page 84
... DAT0 DAT1 ...... DAT7 Figure 44. SD/eMMC4.3 Timing Card Input Clock SD1 Symbols Min Max 400 25/ 20/ 100 400 — — — 3 TLH t — 3 THL t -6.6 3.6 OD Freescale Semiconductor AC Unit kHz MHz MHz kHz ...
Page 85
... Clock Frequency (EMMC4.4 DDR) SD1 Clock Frequency (SD3.0 DDR) uSDHC Output / Card Inputs CMD, DAT (Reference to CLK) SD2 uSDHC Output Delay i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor – 50 MHz. – 52 MHz. Table 58 lists the eMMC4.4 timing characteristics. Be aware ...
Page 86
... ISU t IH Table 59 lists the SDR50/SDR104 timing Figure 46. SDR50/SDR104 Timing Symbols Card Input Clock t CLK t 0.3 0.3 –1 ISU Min Max Unit 2.6 — ns 1.5 — ns Min Max Unit 4.8 — ns 0.7*t ns CLK CLK 0.7*t ns CLK CLK – 2.5 — ns Freescale Semiconductor ...
Page 87
... ENET_RX_ER, and ENET_RX_CLK) The receiver functions correctly ENET_RX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the ENET_RX_CLK frequency. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Symbols Min Max t 1.5 — ...
Page 88
... ENET_TX_CLK frequency. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev Table 60 describes the timing parameters (M1–M4) shown Table 60. MII Receive Signal Timing 1 M4 Min. Max. Unit 5 — — ns 35% 65% ENET_RX_CLK period 35% 65% ENET_RX_CLK period Freescale Semiconductor ...
Page 89
... Table 62. MII Asynchronous Inputs Signal Timing ID Characteristic 1 M9 ENET_CRS to ENET_COL minimum pulse width 1 ENET_COL has the same timing in 10-Mbit 7-wire interface mode. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 61 describes the timing parameters (M5–M8) shown Table 61. MII Transmit Signal Timing 1 Min. ...
Page 90
... ENET_TX_EN, ENET0_TXD[1:0], ENET0_RXD[1:0] and ENET_RX_ER. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev Table 63 describes the timing parameters (M10–M15) M14 M15 M10 M11 M12 M13 Min. 0 — 40% 40% Max. Unit — — ns — ns 60% ENET_MDC period 60% ENET_MDC period Freescale Semiconductor ...
Page 91
... Symbol 2 T Clock cycle duration cyc 3 T Data to clock output skew at transmitter skewT i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 64 describes the timing parameters (M16–M21) shown in the M16 M18 M19 M20 M21 Table 64. RMII Signal Timing Characteristic ...
Page 92
... Tcyc of the lowest speed transitioned between. Figure 52. RGMII Transmit Signal Timing Diagram Original i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev Description will scale to 400 ns ±40 ns and 40 ns ±4 ns respectively. cyc 1 (continued) Min. Max. Unit 1 2 — 0.75 ns Freescale Semiconductor ...
Page 93
... HDMI Module Timing Parameters 4.11.7.1 Latencies and Timing Information Power-up time (time between TX_PWRON assertion and TX_READY assertion) for the HDMI 3D Tx PHY while operating with the slowest input reference clock supported (13.5 MHz) is 3.35 ms. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Electrical Characteristics 93 ...
Page 94
... The table below provides electrical characteristics for the HDMI 3D Tx PHY. The following three figures illustrate various definitions and measurement conditions specified in the table below. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev Figure 55. Driver Measuring Conditions Figure 56. Driver Definitions Figure 57. Source Termination Freescale Semiconductor ...
Page 95
... Hot plug detect time delay t 4.11.8 Switching Characteristics Table 67 describes switching characteristics for the HDMI 3D Tx PHY. various parameters specified in table. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 66. Electrical Characteristics Condition Operating conditions for HDMI - - TMDS drivers DC specifications For measurement conditions and definitions, see the first two figures above ...
Page 96
... All dynamic parameters related to the TMDS line drivers’ performance imply the use of assembly guidelines. Figure 59. Eye Diagram Mask Definition for HDMI Driver Signal Specification at TP1 i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev NOTE Figure 58. TMDS Clock Signal Definitions Figure 60. Intra-Pair Skew Definition Freescale Semiconductor ...
Page 97
... TMDSCLK high time CPH t TMDSCLK low time CPL — TMDSCLK jitter t Intra-pair (pulse) skew SK(p) i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Figure 61. Inter-Pair Skew Definition Table 67. Switching Characteristics Conditions TMDS Drivers Specifications — On TMDSCLKP/N outputs Ω See Figure 58. t ...
Page 98
... IC9 IC3 STOP START Standard Mode Fast Mode Min Max Min 10 — 2.5 4.0 — 0.6 4.0 — 0 3.45 0 4.0 — 0.6 4.7 — 1.3 4.7 — 0.6 Freescale Semiconductor START Unit Max µ — s µ — s µ — µ 0.9 s µ — s µ — s µ — ...
Page 99
... Related image processing and manipulation: sensor image signal processing, display processing, image conversions, and other related functions. • Synchronization and control capabilities, such as avoidance of tearing artifacts. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 2 C Module Timing Parameters (continued) Standard Mode Min 250 4 ...
Page 100
... R/G/B[4] R/G/B[0] Y/C[0] R/G/B[5] R/G/B[1] Y/C[1] R/G/B[0] R/G/B[2] Y/C[2] R/G/B[1] R/G/B[3] Y/C[3] R/G/B[2] R/G/B[4] Y/C[4] R/G/B[3] R/G/B[5] Y/C[5] R/G/B[4] R/G/B[6] Y/C[6] R/G/B[5] R/G/B[7] Y/C[ RGB565 YCbCr YCbCr 16 bits 16 bits 16 bits 2 cycles 1 cycle 1 cycle — — 0 — — 0 — — C[0] — — C[1] B[0] C[0] C[2] B[1] C[1] C[3] B[2] C[2] C[4] B[3] C[3] C[5] B[4] C[4] C[6] G[0] C[5] C[7] G[1] C[6] 0 G[2] C[7] 0 G[3] Y[0] Y[0] G[4] Y[1] Y[1] G[5] Y[2] Y[2] R[0] Y[3] Y[3] R[1] Y[4] Y[4] R[2] Y[5] Y[5] R[3] Y[6] Y[6] R[4] Y[7] Y[7] Freescale Semiconductor 8 YCbCr 20 bits 1 cycle C[0] C[1] C[2] C[3] C[4] C[5] C[6] C[7] C[8] C[9] Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] Y[8] Y[9] ...
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... SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the SENSB_VSYNC timing repeats. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Electrical Characteristics 101 ...
Page 102
... SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 102 Section 4.11.10.2.2, “Gated Clock Figure n+1th frame invalid 1st byte is that of a typical sensor. Some other sensors may have a slightly Mode,”) 65). All incoming pixel clocks are 1st byte Freescale Semiconductor ...
Page 103
... Data and control holdup time 4.11.10.4 IPU Display Interface Signal Mapping The IPU supports a number of display output video formats. Interface Pins used during various supported video interface formats. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor IP2 IP3 Figure 66. Sensor Interface Timing Diagram Symbol ...
Page 104
... The restrictions are as follows: • There are maximal three continuous groups of bits that C[1] could be independently mapped to the external bus. C[2] Groups should not be overlapped. C[3] • The bit order is expressed in each of the bit groups, for C[4] example, B[0] = least significant blue pixel bit C[5] C[6] C[7] C[8] C[9] Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] Y[8] Y[9] — — Freescale Semiconductor ...
Page 105
... This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data during blanking intervals is not supported. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor LCD RGB/TV Signal Allocation (Example) 16-bit ...
Page 106
... When a DI decides to put a new asynchronous data in the bus, a new internal start (local start point) is generated. The signals generators calculate predefined UP and DOWN values to change pins states with half DI_CLK resolution. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 106 NOTE NOTE Freescale Semiconductor ...
Page 107
... VSYNC HSYNC LINE 1 HSYNC DRDY IPP_DISP_CLK IPP_DATA Figure 67. Interface Timing Diagram for TFT (Active Matrix) Panels i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor LINE 2 LINE 3 LINE Electrical Characteristics LINE n-1 LINE n ...
Page 108
... All parameters shown in the figure are programmable. IP13 VSYNC HSYNC DRDY IP11 Figure 69. TFT Panels Timing Diagram—Vertical Sync Pulse i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 108 IP8o IP8 D0 IP9o IP9 IP6 Start of frame IP14 IP12 IP7 IP5 Dn D1 IP10 End of frame IP15 Freescale Semiconductor ...
Page 109
... IP10 Horizontal blank interval 2 IP12 Screen height IP13 VSYNC width IP14 Vertical blank interval 1 IP15 Vertical blank interval 2 i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Figure 68 Symbol Value 1 Tdicp ( ) Display interface clock. Tdpcp DISP_CLK_PER_PIXEL Time of translation of one pixel to display, × ...
Page 110
... DRDY_OFFSET—offset of DRDY edges from a suitable local start point, when a corresponding data has been set on the × bus, in DI_CLK 2 (0.5 DI_CLK Resolution). The DRDY_OFFSET should be built by suitable DI’s counter. DISP_CLK_PERIOD for integer --------------------------------------------------- - DI_CLK_PERIOD for fractional DISP_CLK_PERIOD ---------------------------------------------------- DI_CLK_PERIOD Freescale Semiconductor Unit ...
Page 111
... The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be chip specific. 2 Display interface clock down time i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor ± Accuracy = T 0.62ns ...
Page 112
... GND and IO Supply Voltage Table 75. Electrical and Timing Information Test Conditions Transient voltage range is limited from -300 mV to 1600 mV ⎞ ⎠ Min Max 250 450 1.25 1.6 0.9 1.25 1.15 1.375 -50 50 -24 24 247 454 MIN TYP MAX Unit -50 — 1350 mV Freescale Semiconductor Units ...
Page 113
... Single-ended output OLP(0-11) impedance mismatch driving same level V Differential input high IDTH voltage threshold i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor VGNDSH(min -10 VGNDSH(max) + VOH(absmax) Lane module in LP Receive Mode -50 HS Line Drivers DC Specifications 80 Ω<= RL< = 125 Ω 140 80 Ω ...
Page 114
... Input high voltage IH V Input hysteresis HYST V Input low fault threshold ILF i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 114 LP Line Receiver DC Specifications Contention Line Receiver DC Specifications -70 mV 460 mV - 330 mV Ω 80 125 550 mV 920 200 450 mV Freescale Semiconductor ...
Page 115
... Ideal Differential High Speed Signals 0V (Differential Figure 72. Ideal Single-ended and Resulting Differential HS Signals i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Threshold Region V OHHS Max CMTX,MAX V CMTX,MIN Min OLHS Figure 71. D-PHY Signaling Levels ...
Page 116
... Ω 20 Ω OD (1) MIN TYP MAX 80 — 1000 40 — 500 2 — 25 — 50 — — 1 — — 1 — — 75 — 0.075 0.350 0.650 0.15 0.15 150 0.3UI 150 0.3UI 15 Freescale Semiconductor Unit Mbps MHz pk– rms ...
Page 117
... S R Equivalent wire bond series resistance S R Load resistance L 4.11.12.6 High-Speed Clock Timing CLKp CLKn i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 76. Electrical and Timing Information Test Conditions 80 Ω<= RL< = 125 Ω LP Line Drivers AC Specifications 15% to 85%, C < 30% to 85%, C < 15% to 85%, C < ...
Page 118
... Figure 77. Input Glitch Rejection of Low-Power Receivers i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 118 Reference Time T T SETUP HOLD 0.5UI + INST T SKEW 1 UI INST T CLKp Figure 75. Data to Clock Timing Definitions T TD Clock to Data Skew 2UI 2UI 2*T LPX 2*T LPX e SPIKE T MIN-RX Freescale Semiconductor ...
Page 119
... FLAG N-bits Frame READY Receiver has detected the start of the Frame Figure 80. Receiver Real-Time Data Flow READY Signal Timing i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Last bit of First bit of frame frame Receiver has captured and stored a complete Frame ...
Page 120
... PHY Frame 3. First bit received 4. Received frame stored start state C B: Wake-up state C: Active state (full operational) D PHY Frame 6. Receiver can no longer receive date 5. Transmitter has no more data to transmit D: Disable State(No communication ability) Complete N-bits Frame Complete N-bits Frame Freescale Semiconductor ...
Page 121
... This case shows that the DATA signal has slowed down more compared to the FLAG signal 2 This case shows that the FLAG signal has slowed down more compared to the DATA signal. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Complete N-bits Frame Table 77. DATA and FLAG Timing Description ...
Page 122
... OCM 2 V See Note CMV See Note OS Z — O Receiver Characteristics Min Max Unit — 3.6 V — 0.7 V 1.8 — V — 0.4 V 2.0 — V μA — ±10 Min Max Unit 300 500 mV - 1.0 1 — 150 mVpp — 1.6 — kΩ Freescale Semiconductor ...
Page 123
... MediaLB 3-pin interface, and characteristics. Ground = 0.0 V; Load Capacitance = 60 pF; MediaLB speed = 256/512 Fs kHz; all timing parameters specified from the valid voltage threshold as listed below; unless otherwise noted. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Symbol Test Conditions 4 See Note ...
Page 124
... 256xFs 512xFs ns 256xFs 512xFs ns — ns — — ns — Table 81; unless otherwise noted. Unit Comment MHz 1024xfs at 44.0 kHz 1024xfs at 50.0 kHz — ns — ns — Freescale Semiconductor ...
Page 125
... The transmitting device must ensure valid data on MLBSP/N (MLBDP/N) for at least t BCP/N; receivers must latch MLBSP/N (MLBDP/N) data within t i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Symbol Min Max mcfdz mckl ...
Page 126
... The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external pin. Figure 88 depicts the timing of the PWM, and i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 126 Table 83 lists the PWM timing parameters. Freescale Semiconductor ...
Page 127
... SJC test clock input timing. Figure 91 depicts the SJC test access port. Signal parameters are listed in TCK (Input) SJ3 i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Figure 88. PWM Timing Table 83. PWM Output Timing Parameters Min Figure 90 depicts the SJC boundary scan timing ...
Page 128
... Figure 91. Test Access Port Timing Diagram i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 128 SJ4 Input Data Valid SJ6 Output Data Valid SJ7 SJ6 Output Data Valid SJ8 Input Data Valid SJ10 Output Data Valid SJ11 SJ10 Output Data Valid VIH SJ5 VIH SJ9 Freescale Semiconductor ...
Page 129
... Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SRCK) for SPDIF in Rx mode and the timing of the modulating Tx clock (STCLK) for SPDIF in Tx mode. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor SJ13 Figure 92. TRST Timing Diagram Table 84. JTAG Timing ...
Page 130
... Figure 93. SRCK Timing Diagram stclkp stclkpl stclkph Figure 94. STCLK Timing Diagram Timing Parameter Range Min Max — 0.7 — 1.5 — 24.2 — 31.3 — 1.5 — 13.6 — 18.0 40.0 — 16.0 — 16.0 — 40.0 — 16.0 — 16.0 — Freescale Semiconductor Unit ...
Page 131
... Reference Manual (IMX6SDLRM)are channel specific signal names. For example, a channel clock referenced in the IOMUXC chapter as AUD3_TXC appears in the timing diagram as RGMII_TXC. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 86. Table 86. AUDMUX Port Allocation Type and Access ...
Page 132
... SS1 SS5 SS4 SS8 SS10 SS14 SS16 SS17 SS43 SS42 Parameter Internal Clock Operation lists the timing parameters for SS3 SS12 SS15 SS18 SS19 Min Max Unit 81.4 — ns 36.0 — ns 36.0 — ns — 15.0 ns — 15.0 ns — 15.0 ns — 15.0 ns — 6.0 ns — 6.0 ns — 15.0 ns — 15.0 ns — 15.0 ns Freescale Semiconductor ...
Page 133
... Transmit and Receive sections of the SSI. • For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Parameter Synchronous Internal Clock Operation NOTE Electrical Characteristics ...
Page 134
... SS51 SS47 SS50 Parameter Internal Clock Operation Oversampling Clock Operation lists the timing parameters for the SS3 SS13 SS21 SS49 Min Max 81.4 — 36.0 — — 6.0 36.0 — — 6.0 — 15.0 — 15.0 — 15.0 — 15.0 10.0 — 0.0 — Freescale Semiconductor Unit ...
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... The terms, WL and BL, refer to Word Length (WL) and Bit Length (BL). • For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Parameter NOTE Electrical Characteristics Min Max Unit 15 ...
Page 136
... Table 89 SS22 SS25 SS26 SS27 SS29 SS31 SS37 SS44 Parameter External Clock Operation lists the timing parameters for SS24 SS33 SS39 SS38 SS45 SS46 Min Max Unit 81.4 — ns 36.0 — ns — 6.0 ns 36.0 — ns — 6.0 ns -10.0 15.0 ns 10.0 — ns -10.0 15.0 ns 10.0 — ns — 15.0 ns — 15.0 ns Freescale Semiconductor ...
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... The terms WL and BL refer to Word Length (WL) and Bit Length (BL). • For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Parameter Synchronous External Clock Operation NOTE Electrical Characteristics ...
Page 138
... SS32 SS35 SS40 Parameter External Clock Operation lists the timing parameters for the SS24 SS34 SS41 SS36 Min Max Unit 81.4 — — ns — 6 — ns — 6.0 ns -10 15 — ns -10 15 — ns — 6.0 ns — 6 — — ns Freescale Semiconductor ...
Page 139
... Output Serial data from DTE to DCE 4.11.20.2 UART RS-232 Serial Mode Timing The following sections describe the electrical information of the UART module in the RS-232 mode. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor NOTE Table 91. UART I/O Configuration vs. Mode DTE Mode Description ...
Page 140
... Parity Bit Next Start STOP Bit 7 Par Bit Bit BIT UA1 UA1 Max Unit 1 - 1/F + — baud_rate 2 T ref_clk Table 93 lists Possible Parity Bit Next Start STOP Bit 7 Par Bit Bit BIT UA2 UA2 Max Unit 2 - 1/(16 1/F + — baud_rate ) 1/( baud_rate Freescale Semiconductor ...
Page 141
... Figure 102. UART IrDA Mode Receive Timing Diagram Table 95. IrDA Mode Receive Timing Parameters ID Parameter 1 UA5 Receive Bit Time in IrDA mode UA6 Receive IR Pulse Duration i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor UA3 Bit 1 Bit 2 Bit 3 Bit 4 Symbol t TIRbit t (3/16) x (1/F ...
Page 142
... But accumulation tolerance in one frame must not baud_rate NOTE Tstrobe Todelay Figure 103. USB HSIC Transmit Waveform Table 96. USB HSIC Transmit Parameters Min Max Unit 4.166 4.167 ns 550 1350 ps 0.7 2 V/ns Todelay Comment Measured at 50% point Averaged from 30% – 70% points Freescale Semiconductor ...
Page 143
... USB ENGINEERING CHANGE NOTICE — Title: Suspend Current Limit Changes — Applies to: Universal Serial Bus Specification, Revision 2.0 i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Tstrobe Thold Tsetup Figure 104. USB HSIC Receive Waveform Table 97. USB HSIC Receive Parameters ...
Page 144
... Fuse Map document and the System Boot chapter in i.MX 6Solo/6DualLite Reference Manual (IMX6SDLRM). Table 98. Fuses and Associated Pins Used for Boot Pin Direction at Reset BOOT_MODE1 BOOT_MODE0 i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 144 eFuse Name Input N/A Input N/A Details Boot Mode selection Boot Mode Selection Freescale Semiconductor ...
Page 145
... EIM_A17 EIM_A18 EIM_A19 EIM_A20 EIM_A21 EIM_A22 EIM_A23 EIM_A24 EIM_WAIT EIM_LBA EIM_EB0 EIM_EB1 EIM_RW EIM_EB2 EIM_EB3 i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor eFuse Name Input BOOT_CFG1[0] Input BOOT_CFG1[1] Input BOOT_CFG1[2] Input BOOT_CFG1[3] Input BOOT_CFG1[4] Input BOOT_CFG1[5] Input BOOT_CFG1[6] Input ...
Page 146
... Table 99. Interface Allocation During Boot Allocated Pads During Boot Comment Used for NOR, OneNAND boot Only CS0 is supported 8 bit Only CS0 is supported bit bit bit bit — — — — Freescale Semiconductor ...
Page 147
... This section includes the contact assignment information and mechanical package drawing. 6.1 21x21 mm Package Information 6.1.1 Case 2240 mm, 0.8 mm Pitch Ball Matrix Figure 105 shows the top, bottom, and side views of the 21×21 mm BGA package. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 147 ...
Page 148
... Package Information and Contact Assignments i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 148 Freescale Semiconductor ...
Page 149
... Figure 105 BGA, Case 2240 Package Top, Bottom, and Side Views i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 149 ...
Page 150
... Supply of the LCD interface Supply of the LVDS display interface and DDR pre-drivers Supply of the MIPI interface Supply of the raw NAND Flash memories interface Supply of the ENET interface Supply of the SD card interface Supply of the SD card interface Supply of the SD card interface Freescale Semiconductor ...
Page 151
... VDD_FA B5 ZQPAD AE17 NC C14 NC G12 i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments Ball(s) Position(s) Remark PCI PHY supply PCI PHY supply Secondary supply for the SNVS (internal regulator output—requires capacitor if internal regulator is used) ...
Page 152
... Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Freescale Semiconductor ...
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... NVCC_LCD DISP0_DAT20 U22 NVCC_LCD DISP0_DAT21 T20 NVCC_LCD DISP0_DAT22 V24 NVCC_LCD DISP0_DAT23 W24 NVCC_LCD i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 1 Out of Reset Condition Ball Default Type Mode Default Function (Reset Mode) GPIO ALT5 gpio5.GPIO[24] ...
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... Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Freescale Semiconductor ...
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... NVCC_DRAM DRAM_D36 Y17 NVCC_DRAM DRAM_D37 Y18 NVCC_DRAM DRAM_D38 AB19 NVCC_DRAM DRAM_D39 AC19 NVCC_DRAM i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 1 Out of Reset Condition Ball Default Type Mode Default Function (Reset Mode) DDR ALT0 mmdc.DRAM_D[12] ...
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... Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Freescale Semiconductor ...
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... DRAM_SDQS2_B AE8 NVCC_DRAM DRAM_SDQS3 AC10 NVCC_DRAM DRAM_SDQS3_B AB10 NVCC_DRAM DRAM_SDQS4 AD18 NVCC_DRAM i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition Ball Default Type Mode Default Function (Reset Mode) DDR ALT0 mmdc.DRAM_DQM[0] DDR ALT0 mmdc ...
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... Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output High Output High Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Freescale Semiconductor ...
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... NVCC_EIM EIM_DA7 L25 NVCC_EIM EIM_DA8 L24 NVCC_EIM EIM_DA9 M21 NVCC_EIM EIM_EB0 K21 NVCC_EIM i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 1 Out of Reset Condition Ball Default Type Mode Default Function (Reset Mode) GPIO ALT5 gpio3.GPIO[19] ...
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... Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Freescale Semiconductor ...
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... KEY_ROW4 V5 NVCC_GPIO LVDS0_CLK_N V4 NVCC_LVDS2P5 LVDS0_CLK_P V3 NVCC_LVDS2P5 LVDS0_TX0_N U2 NVCC_LVDS2P5 LVDS0_TX0_P U1 NVCC_LVDS2P5 i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 1 Out of Reset Condition Ball Default Type Mode Default Function (Reset Mode) GPIO ALT5 gpio1.GPIO[9] GPIO ALT0 sjc.MOD ...
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... Keeper Input Keeper Input Keeper Input Keeper Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Freescale Semiconductor ...
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... NVCC_RGMII RGMII_TD2 E21 NVCC_RGMII RGMII_TD3 A24 NVCC_RGMII RGMII_TX_CTL C23 NVCC_RGMII RGMII_TXC D21 NVCC_RGMII i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 1 Out of Reset Condition Ball Default Type Mode Default Function (Reset Mode) GPIO ALT5 gpio2.GPIO[2] ...
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... Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Freescale Semiconductor ...
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... DRAM_D32 to DRAM_D63 are only available for i.MX 6DualLite chip; for i.MX 6Solo chip, these pins are NC. 2 The state immediately after reset and before ROM firmware or software has executed. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 1 Out of Reset Condition ...
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... Package Information and Contact Assignments 6.1 mm, 0.8 mm Pitch Ball Map Table 102 shows the mm, 0.8 mm pitch ball map for the i.MX 6Solo. Table 102 mm, 0.8 mm Pitch Ball Map i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 166 Freescale Semiconductor ...
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... Table 102 mm, 0.8 mm Pitch Ball Map (continued) i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 167 ...
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... Package Information and Contact Assignments Table 102 mm, 0.8 mm Pitch Ball Map (continued) i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 168 Freescale Semiconductor ...
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... Table 102 mm, 0.8 mm Pitch Ball Map (continued) Table 103 shows the mm, 0.8 mm pitch ball map for the i.MX 6DualLite. Table 103 mm, 0.8 mm Pitch Ball Map i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 169 ...
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... Package Information and Contact Assignments Table 103 mm, 0.8 mm Pitch Ball Map (continued) i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 170 Freescale Semiconductor ...
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... Table 103 mm, 0.8 mm Pitch Ball Map (continued) i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 171 ...
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... Package Information and Contact Assignments Table 103 mm, 0.8 mm Pitch Ball Map (continued) i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 172 Freescale Semiconductor ...
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... Table 83, "PWM Output Timing Parameters," on page • Updated Section 4.11.22, “USB PHY Parameters.” Rev. 0 10/2012 Initial public release. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Substantive Change(s) 3. added a footnote on the bottom of page 6 to specify performance limitation 22, added details of VDD_SNVS_IN parameter. 24. ...
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... Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. ARM is the registered trademark of ARM Limited. ARM Cortex™- trademark of ARM Limited. © ...