E909.05A61DC ELMOS Semiconductor, E909.05A61DC Datasheet - Page 21

• Manufacturer Part Number: E909.05A61DC
• Description: Processors - Application Specialized Halios multipurpose sensor IC
• Manufacturer: ELMOS Semiconductor

Specifications of E909.05A61DC

• Rohs: yes
• Processor Series: EL16
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 8 MHz
• Data Ram Size: 3 kB
• Operating Supply Voltage: 2.25 V to 2.75 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Interface Type: I2C, SPI
• Memory Type: Flash, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

PRELIMINARY INFORMATION AUG 02, 2011
Register Current Configuration Phase A (0x04)
Table 5.6.3.4: Current Configuration Phase A
Register Current Configuration Phase B (0x06)
Table 5.6.3.5: Current Configuration Phase B
Transmitting current LED1-4:
In the regulated mode (FIXA/B = '0') the total current is
In constant mode (FIXA = '1' or FIXB = '1'):
where I
parasitic effects.
Register Current Configuration Compensator Offset (0x08)
Table 5.6.3.6: Current Configuration Compensator Offset
The offset current for the terminal LEDC is configureable with the seven bit value OFFSET.
This document contains information on a pre-production product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice.
ELMOS Semiconductor AG
Content
Reset value
Internal access
External access R
Bit Description
Content
Reset value
Internal access
External access R
Bit Description
Content
Reset value
Internal access
External access R
Bit Description
HALIOS® MULTI-PURPOSE OPTICAL SENSOR WITH HIGH LIGHT IMMUNITY
BIAS S
I
I
total
total
is a small current which always keeps the LEDs turned on to maximise speed and minimise
=I
=I
MSB
0
R
9:5 : OFF: Offset phase A
4:0 : RNG: Range phase A
MSB
0
R
9:5 : OFF: OFFSET phase B
4:0 : RNG: RANGE phase B
MSB
0
R
11:8 : DC_OFFSET current LEDC (4 Bit)
6:0 : OFFSET compensation LEDC
OFFSET
OFFSET
15
15
15


0
R
R
14
0
R R
R R
0
R R
R R
14 13
14 13
I
I
REGULATE
RANGE
1023
0
0
2
0
R
R
13
 I
0
R
R
0
R
R
0
R
R
12
12
⋅I
12
BIAS S
RANGE
0
R
R
0
R
R
0
R/W R/W R/W R/W R
R/W R/W R/W R/W R
11
11
11
 I
Data Sheet 21 / 67
0
R
R
0
R
R
0
10
10
10
BIAS S
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0
9
9
9
0
0
0
8
8
8
, with I
I
I
OFFSET
RANGE
0
0
0
7
7
7
= RANGE
= OFFSET
REGULATE
0
0
0
R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W
6
6
6
0
0
0
= 0 ... 1023 (10 bit DAC)
5
5
5
*
*
I
R_STEPS
I
O_STEPS
0
0
0
4
4
4
QM-No.: 25DS0014E.00
0
0
0
3
3
3
0
0
0
2
2
2
E909.05
0
0
0
1
1
1
LSB
0
LSB
0
LSB
0
0
0
0