MCIMX6S5DVM10AB Freescale Semiconductor, MCIMX6S5DVM10AB Datasheet - Page 87

• Manufacturer Part Number: MCIMX6S5DVM10AB
• Description: Processors - Application Specialized i.MX6 Solo rev 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6S5DVM10AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 256 kB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Mounting Style: SMD/SMT
• Package / Case: FCBGA-624
• Interface Type: I2C, I2S, SDIO, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM

Figure 46
in the figure.
1
4.11.5.1.3
Figure 47
the figure.
1
Freescale Semiconductor
M9
ENET_TX_EN, ENET_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.
ENET_COL has the same timing in 10-Mbit 7-wire interface mode.
M5
M6
M7
M8
1
ID
ENET_TX_DATA3,2,1,0
ID
ENET_TX_CLK (input)
ENET_CRS to ENET_COL minimum pulse width
shows MII asynchronous input timings.
shows MII transmit signal timings.
ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER invalid
ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER valid
ENET_TX_CLK pulse width high
ENET_TX_CLK pulse width low
ENET_CRS, ENET_COL
ENET_TX_EN
ENET_TX_ER
MII Asynchronous Inputs Signal Timing (ENET_CRS and ENET_COL)
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1
(outputs)
Table 58. MII Asynchronous Inputs Signal Timing
Characteristic
Figure 46. MII Transmit Signal Timing Diagram
Characteristic
Figure 47. MII Async Inputs Timing Diagram
Table 57. MII Transmit Signal Timing
1
Table 57
M5
Table 58
M6
M7
describes the timing parameters (M5–M8) shown
describes the timing parameter (M9) shown in
M9
Min.
Min.
35%
35%
1.5
—
5
M8
Max.
Max.
65%
65%
—
20
—
ENET_TX_CLK period
ENET_TX_CLK period
Electrical Characteristics
ENET_TX_CLK period
Unit
ns
ns
Unit
87