MCIMX6S5DVM10AB Freescale Semiconductor, MCIMX6S5DVM10AB Datasheet - Page 19

• Manufacturer Part Number: MCIMX6S5DVM10AB
• Description: Processors - Application Specialized i.MX6 Solo rev 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6S5DVM10AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 256 kB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Mounting Style: SMD/SMT
• Package / Case: FCBGA-624
• Interface Type: I2C, I2S, SDIO, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM

3.1
Table 3
listed in alphabetical order.
The package contact assignments can be found in
Assignments.”
(IMX6SDLRM).
Freescale Semiconductor
RTC_XTALI/RTC_XTALO If the user wishes to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz
CLK1_P/CLK1_N
CLK2_P/CLK2_N
XTALI/XTALO
Signal Name
lists special signal considerations for the i.MX 6Solo/6DualLite processors. The signal names are
Special Signal Considerations
Signal descriptions are provided in the i.MX 6Solo/6DualLite Reference Manual
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1
Two general purpose differential high speed clock Input/outputs are provided.
Any or both of them could be used:
See the i.MX 6Solo/6DualLite reference manual for details on the respective clock trees.
The clock inputs/outputs are LVDS differential pairs compatible with TIA/EIA-644 standard, the
maximal frequency range supported is 0...600 MHz.
Alternatively one may use single ended signal to drive CLKx_P input. In this case corresponding
CLKx_N input should be tied to the constant voltage level equal 1/2 of the input signal swing.
Termination should be provided in case of high frequency signals.
See LVDS pad electrical specification for further details.
After initialization, the CLKx inputs/outputs could be disabled (if not used). If unused any or both of
the CLKx_N/P pairs may be left floating.
crystal, (≤100 kΩ ESR, 10 pF load) should be connected between RTC_XTALI and RTC_XTALO.
Keep in mind the capacitors implemented on either side of the crystal are about twice the crystal
load capacitor. To hit the exact oscillation frequency, the board capacitors need to be reduced to
account for board and chip parasitics. The integrated oscillation amplifier is self biasing, but
relatively weak. Care must be taken to limit parasitic leakage from RTC_XTALI and RTC_XTALO
to either power or ground (>100 MΩ). This will debias the amplifier and cause a reduction of startup
margin. Typically RTC_XTALI and RTC_XTALO should bias to approximately 0.5 V.
If it is desired to feed an external low frequency clock into RTC_XTALI the RTC_XTALO pin should
be left floating or driven with a complimentary signal. The logic level of this forcing clock should not
exceed VDD_SNVS_CAP level and the frequency should be <100 kHz under typical conditions.
In case when high accuracy real time clock are not required system may use internal low frequency
ring oscillator. It is recommended to connect RTC_XTALI to GND and keep RTC_XTALO floating.
should be <32 MHz under typical conditions.
The crystal must be rated for a maximum drive level of 250 μW. An ESR (equivalent series
resistance) of typical 80 Ω is recommended. Freescale BSP (board support package) software
requires 24 MHz on XTALI/XTALO.
The crystal can be eliminated if an external 24 MHz oscillator is available in the system. In this
case, XTALI must be directly driven by the external oscillator and XTALO is floated. The XTALI
signal level must swing from ~0.8 x NVCC_PLL_OUT to ~0.2 V.
If this clock is used as a reference for USB and PCIe, then there are strict frequency tolerance and
jitter requirements. See OSC24M chapter and relevant interface specifications chapters for details.
A 24.0 MHz crystal should be connected between XTALI and XTALO. level and the frequency
• To feed external reference clock to the PLLs and further to the modules inside SoC, for example
• To output internal SoC clock to be used outside the SoC as either reference clock or as a
as alternate reference clock for PCIe, Video/Audio interfaces, etc.
functional clock for peripherals, for example it could be used as an output of the PCIe master
clock (root complex use)
Table 3. Special Signal Considerations
Section 6, “Package Information and Contact
Remarks
Modules List
19