MCIMX6S5DVM10AB Freescale Semiconductor, MCIMX6S5DVM10AB Datasheet - Page 110

• Manufacturer Part Number: MCIMX6S5DVM10AB
• Description: Processors - Application Specialized i.MX6 Solo rev 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6S5DVM10AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 256 kB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Mounting Style: SMD/SMT
• Package / Case: FCBGA-624
• Interface Type: I2C, I2S, SDIO, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM

3
Electrical Characteristics
4.11.11 LVDS Display Bridge (LDB) Module Parameters
The LVDS interface complies with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD
644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits”.
4.11.12 MIPI D-PHY Timing Parameters
This section describes MIPI D-PHY electrical specifications, compliant with MIPI CSI-2 version 1.0,
D-PHY specification Rev. 1.0 (for MIPI sensor port x2 lanes) and MIPI DSI Version 1.01, and D-PHY
specification Rev. 1.0 (and also DPI version 2.0, DBI version 2.0, DSC version 1.0a at protocol layer) (for
MIPI display port x2 lanes).
4.11.12.1 Electrical and Timing Information
110
Differential Voltage Output Voltage
Output Voltage High
Output Voltage Low
Offset Static Voltage
VOS Differential
Output short circuited to GND
VT Full Load Test
Display interface clock up time where CEIL(X) rounds the elements of X to the nearest integers towards infinity.
V
I
Symbol
Parameter
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1
Input signal voltage range
Table 70. LVDS Display Bridge (LDB) Electrical Specification
Parameters
Input DC Specifications - Apply to CLKP/N and DATAP/N inputs
Table 71. Electrical and Timing Information
Symbol
V
ISA ISB With the output common shorted to GND
VTLoad 100 Ω Differential load with a 3.74 kΩ load between
OSDIFF
Tdicu
V
Voh
V
Vol
OD
OS
=
100 Ω Differential load
100 Ω differential load (0 V Diff—Output High
Voltage static)
100 Ω differential load (0 V Diff—Output Low
Voltage static)
Two 49.9 Ω resistors in series between N-P
terminal, with output in either Zero or One state, the
voltage measured between the 2 resistors.
Difference in V
GND and IO Supply Voltage
1
-- - T diclk
2
⎛
⎝
is limited from -300 mV to
Transient voltage range
Test Conditions
×
1600 mV
ceil
OS
2
----------------------------------------------- -
Test Condition
DI_CLK_PERIOD
between a One and a Zero state
×
DISP_CLK_UP
MIN
-50
⎞
⎠
TYP
—
Freescale Semiconductor
1.25
1.15
Min
250
247
0.9
-50
-24
MAX
1350
1.375
Max
1.25
mV
450
454
1.6
50
24
Unit
Units
mV
mV
mV
mV
mA
mV
V