MCIMX6Q6AVT10AC Freescale Semiconductor, MCIMX6Q6AVT10AC Datasheet - Page 16

• Manufacturer Part Number: MCIMX6Q6AVT10AC
• Description: Processors - Application Specialized i.MX6Q
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6Q6AVT10AC

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 16 KB
• Operating Supply Voltage: 1.05 V to 1.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FCBGA
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

Modules List
16
Mnemonic
uSDHC-1
uSDHC-2
uSDHC-2
uSDHC-4
WDOG-1
VDOA
Block
VPU
SD/MMC and SDXC
Enhanced
Multi-Media Card /
Secure Digital Host
Controller
VDOA
Video Processing
Unit
Watchdog
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
Block Name
Table 2. i.MX 6Dual/6Quad Modules List (continued)
Connectivity
Peripherals
Multimedia
Peripherals
Multimedia
Peripherals
Timer
Peripherals
Subsystem
i.MX 6Dual/6Quad specific SoC characteristics:
All four MMC/SD/SDIO controller IPs are identical and are based on the
uSDHC IP. They are:
All four ports support:
However, the SoC-level integration and I/O muxing logic restrict the
functionality to the following:
The Video Data Order Adapter (VDOA) is used to re-order video data
from the “tiled” order used by the VPU to the conventional raster-scan
order needed by the IPU.
A high-performing video processing unit (VPU), which covers many
SD-level and HD-level video decoders and SD-level encoders as a
multi-standard video codec engine as well as several important video
processing, such as rotation and mirroring.
See the i.MX 6Dual/6Quad reference manual (IMX6DQRM) for complete
list of VPU’s decoding/encoding capabilities.
The Watchdog Timer supports two comparison points during each
counting period. Each of the comparison points is configurable to evoke
an interrupt to the ARM core, and a second point evokes an external
event on the WDOG line.
• Fully compliant with MMC command/response sets and Physical Layer
• Fully compliant with SD command/response sets and Physical Layer
• Fully compliant with SDIO command/response sets and
• Fully compliant with SD Card Specification, Part A2, SD Host
• 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to
• 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to
• Instances #1 and #2 are primarily intended to serve as external slots
• Instances #3 and #4 are primarily intended to serve interfaces to
• All ports can work with 1.8 V and 3.3 V cards. There are two
as defined in the Multimedia Card System Specification,
v4.2/4.3/4.4/4.41 including high-capacity (size > 2 GB) cards HC
MMC. Hardware reset as specified for eMMC cards is supported at
ports #3 and #4 only.
as defined in the SD Memory Card Specifications, v3.0 including
high-capacity SDHC cards up to 32 GB.
interrupt/read-wait mode as defined in the SDIO Card Specification,
Part E1, v1.10
Controller Standard Specification, v2.00
UHS-I SDR104 mode (104 MB/s max)
52 MHz in both SDR and DDR modes (104 MB/s max)
or interfaces to on-board SDIO devices. These ports are equipped with
“Card Detection” and “Write Protection” pads and do not support
hardware reset.
embedded MMC memory or interfaces to on-board SDIO devices.
These ports do not have “Card detection” and “Write Protection” pads
and do support hardware reset.
completely independent I/O power domains for Ports #1 and #2 in four
bit configuration (SD interface). Port #3 is placed in his own
independent power domain and port #4 shares power domain with
some other interfaces.
Brief Description
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