MCIMX6Q6AVT10AC Freescale Semiconductor, MCIMX6Q6AVT10AC Datasheet - Page 101
MCIMX6Q6AVT10AC
Manufacturer Part Number
MCIMX6Q6AVT10AC
Description
Processors - Application Specialized i.MX6Q
Manufacturer
Freescale Semiconductor
Type
Multimedia Applicationsr
Datasheet
1.MCIMX6Q6AVT10AC.pdf
(166 pages)
Specifications of MCIMX6Q6AVT10AC
Rohs
yes
Core
ARM Cortex A9
Processor Series
i.MX6
Data Bus Width
32 bit
Maximum Clock Frequency
1 GHz
Data Ram Size
16 KB
Operating Supply Voltage
1.05 V to 1.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
FCBGA
Interface Type
I2C, I2S, UART, USB
Memory Type
L1/L2 Cache, ROM, SRAM
Minimum Operating Temperature
- 40 C
Number Of Timers
2
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4.11.10.5 IPU Display Interface Timing
The IPU Display Interface supports two kinds of display accesses: synchronous and asynchronous. There
are two groups of external interface pins to provide synchronous and asynchronous controls.
4.11.10.5.1 Synchronous Controls
The synchronous control changes its value as a function of a system or of an external clock. This control
has a permanent period and a permanent waveform.
There are special physical outputs to provide synchronous controls:
Freescale Semiconductor
i.MX 6Dual/6Quad
This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line
start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data
during blanking intervals is not supported.
IPUx_DIx_D0_CS
IPUx_DIx_D1_CS
• A maximum of three continuous groups of bits can be independently mapped to the external bus. Groups must not overlap.
• The bit order is expressed in each of the bit groups, for example, B[0] = least significant blue pixel bit.
IPUx_DIx_PIN11
IPUx_DIx_PIN12
IPUx_DIx_PIN13
IPUx_DIx_PIN14
IPUx_DIx_PIN15
IPUx_DIx_PIN16
IPUx_DIx_PIN17
Signal mapping (both data and control/synchronization) is flexible. The table provides examples.
Restrictions for ports IPUx_DISPx_DAT00 through IPUx_DISPx_DAT23 are as follows:
•
Port Name
(x = 0, 1)
The ipp_disp_clk is a dedicated base synchronous signal that is used to generate a base display
(component, pixel) clock for a display.
Table 69
However, DISP1 port has reduced pinout depending on IOMUXC
configuration and therefore may not support all configurations. See the
IOMUXC table for details.
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
(General)
Signal
Name
RGB,
provides information for both the DISP0 and DISP1 ports.
Table 69. Video Signal Cross-Reference (continued)
16-bit
RGB
RGB/TV Signal Allocation (Example)
18-bit
RGB
DRDY/DV
24 Bit
LCD
RGB
—
—
—
—
—
—
—
Q
NOTE
YCrCb
8-bit
3
YCrCb
16-bit
YCrCb
20-bit
Alternate mode of PWM output for
contrast or brightness control
Register select signal
Optional RS2
Data validation/blank, data enable
Additional data synchronous
signals with programmable
features/timing
Electrical Characteristics
Comment
—
—
—
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