XRT83SL216ES Exar, XRT83SL216ES Datasheet - Page 35

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XRT83SL216ES

Manufacturer Part Number
XRT83SL216ES
Description
Peripheral Drivers & Components - PCIs 16 CH E1 LIU SH
Manufacturer
Exar
Datasheet

Specifications of XRT83SL216ES

Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
REV. 1.0.0
(0
X
06
B
D5
D4
D3
D2
D1
D0
H
IT
, 0
X
09
H
RCLKinv_n Receiver Clock Invert
TCLKinv_n Transmit Clock Invert
, 0
ATAOS_n
RLAM_n
TXOE_n
TAOS_n
N
X
0C
AME
H
, 0
X
0F
Automatic Transmit All Ones
If ATAOS_n is selected, an all ones pattern will be transmitted from
TTIP/TRING if the channel experiences an RLOS condition. If
RLOS does not occur, ATAOS_n will remain inactive.
"0" = Disabled
"1" = Enabled
Transmit All Ones
If TAOS_n is selected, an all ones pattern will be transmitted from
TTIP/TRING if the transmitter is turned on. Remote Loop Back
has priority over TAOS.
"0" = Disabled
"1" = Enabled
RLOS/AIS Mode Select for channel n
This bit is used to select the industry standard for declaring / clear-
ing RLOS and AIS functionality. See the Receive section of the
Line Interface description.
"0" = ITU G.775
"1" =ETSI300233
Transmit Output Enable
Upon power up, the tranmitters are tri-stated. This bit is used to
enable the transmitter for this channel if the TxOE pin is pulled
"High". If the TxOE pin is pulled "Low", all 8 transmitters are tri-
stated.
"0" = Transmitter is disabled
"1" = Transmitter is enabled if TxOE pin is pulled "High"
This bit is used to invert receive clock update edge with respect to
RPOS/RNEG output data.
"0" =RPOS/RNEG data is updated on the rising edge of RCLK
"1" =RPOS/RNEG data is updated on the falling edge of RCLK.
This bit is used to invert transmit clock sampling edge with respect
to TPOS/TNEG input data.
"0" =TPOS/TNEG data is sampled on the falling edge of TCLK
"1" =TPOS/TNEG data is sampled on the rising edge of TCLK.
H
T
, 0
C
ABLE
HANNEL
X
12
H
11: M
, 0
C
X
15
ONTROL
ICROPROCESSOR
H
, 0
X
18
R
H
EGISTER
, 0
X
F
16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
1B
UNCTION
33
H
(C
, 1E
R
HANNEL
EGISTER
H
, 0
X
21
_n, where n = 0:15)
H
B
, 0
IT
X
D
24
ESCRIPTION
H
, 0
X
27
H
, 0
X
2A
H
, 0
Register
Type
R/W
R/W
R/W
R/W
R/W
R/W
X
2D
XRT83SL216
H
, 0
X
30
(HW reset)
H
Default
Value
, 0X33
0
0
0
0
0
0
0
H
)

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