XRT83SL216ES Exar, XRT83SL216ES Datasheet - Page 33

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XRT83SL216ES

Manufacturer Part Number
XRT83SL216ES
Description
Peripheral Drivers & Components - PCIs 16 CH E1 LIU SH
Manufacturer
Exar
Datasheet

Specifications of XRT83SL216ES

Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
REV. 1.0.0
B
B
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
IT
IT
JASEL1
JASEL0
INTS_n
JABW
N
N
AME
AME
T
ABLE
T
JA Band width Select
This bit is used to select the band with of the JA PLL.
"0" = 10 Hz "1" = 1.5Hz
N
Jitter Attenuator Select
These bits are used to configure the Jitter Attenuator into the
Receive or Transmit path.
"00" = Disabled
"01" = Transmit Path
"10" = Receive Path
"11" = Disabled
Interrupt Status
These 2 registers are ready only to determine when an interrupt
event occurs, the channel that generates interrupt can be identified
with minimum read/write operation.
ABLE
8: M
OTE
G
LOBAL
: If a "1" is written into this bit, JA FIFO size of 64 bit wide is
ICROPROCESSOR
7: M
automatically selected.
I
NTERRUPT
ICROPROCESSOR
C
ONTROL
S
R
TATUS
EGISTER FOR
R
EGISTERS
F
F
16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
R
UNCTION
UNCTION
R
EGISTERS
EGISTER
31
A
0
LL
X
01
(0
16 C
0
X
X
H
01
00
&0
H
HANNELS
H
) & 0
X
B
02
IT
X
H
02
D
B
ESCRIPTION
(0
H
IT
X
00
D
ESCRIPTION
H
)
Register
Register
Type
Type
R/W
R/W
RO
XRT83SL216
(HW reset)
(HW reset)
Default
Default
Value
Value
0
0
0
0
0
0
0
0
0
0
0

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