74ABT374CMSA_Q Fairchild Semiconductor, 74ABT374CMSA_Q Datasheet
74ABT374CMSA_Q
Specifications of 74ABT374CMSA_Q
Related parts for 74ABT374CMSA_Q
74ABT374CMSA_Q Summary of contents
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... Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.5.0 General Description The ABT374 is an octal D-type flip-flop featuring sepa- rate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications ...
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... Operation of the OE input does not affect the state of the flip-flops. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.5.0 Pin Descriptions Pin Names Description D – ...
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... Free Air Ambient Temperature A V Supply Voltage Minimum Input Edge Rate Data Input Enable Input Clock Input ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.5.0 Parameter Parameter 3 Rating –65°C to +150°C –55°C to +125°C –55°C to +150°C –0.5V to +7.0V –0.5V to +7.0V – ...
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... Outputs Enabled CCT I /Input CC Outputs 3-STATE Outputs 3-STATE I Dynamic I No Load CCD CC Notes: 2. For 8-bit toggling, I 0.8mA/MHz. CCD 3. Guaranteed, but not tested. ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.5.0 V Conditions CC Recognized HIGH Signal Recognized LOW Signal Min. I –18mA IN Min. I –3mA OH I –32mA OH Min ...
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... SOIC and SSOP package. Symbol Parameter f Maximum Clock MAX Frequency t Propagation Delay PLH PHL t Output Enable Time PZH t PZL t Output Disable Time PHZ t PLZ ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.5.0 Conditions 5.0 T 25° 5.0 T 25° 5.0 T 25°C A 5.0 T 25° ...
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... LOW-to-HIGH, HIGH-to-LOW, etc.) with 250pF load capacitors in place of the 50pF load capacitors in the standard AC load. 10. The 3-STATE delay Time is dominated by the RC network (500 , 250pF) on the output and has been excluded from the datasheet. ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.5.0 T +25°C T – ...
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... This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Capacitance Symbol Parameter C Input Capacitance IN (16) C Output Capacitance OUT Note: 16 measured at frequency f OUT ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.5.0 T –40°C to +85° 4.5V–5. (11) 8 Outputs Switching Max. 1.0 1.0 1 ...
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... AC Loading *Includes jig and probe capacitance Figure 1. Standard AC Test Load Amplitude Rep. Rate AC Waveforms Figure 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions Figure 5. Propagation Delay, Pulse Width Waveforms ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.5.0 Input Pulse Requirements t w 3.0V 1 MHz 500ns Figure 3 ...
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... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...
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... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...
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... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...
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... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...
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... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...