DS32506W Maxim Integrated, DS32506W Datasheet - Page 84

• Manufacturer Part Number: DS32506W
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32506W

• Part # Aliases: 90-32506-W00

9.8 BERT Registers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 7: Performance Monitoring Update Mode (PMUM). This bit specifies the source of the performance
monitoring update signal for the BERT block. See Section 8.7.4. Note: If RPMU or LPMU is one, changing the state
of this bit may cause a performance monitoring update to occur.
Bit 6: Local Performance Monitoring Update (LPMU). When BERT.CR:PMUM = 0, this bit updates the
performance monitoring registers in the BERT block. When this bit transitions from low to high, the
and
remain high until the performance monitor update status bit (BERT.SR:PMS) goes high, and then it should be
brought back low, which clears the PMS status bit. If a counter increment occurs at the exact same time as the
counter reset, the counter is loaded with a value of one, and the “counter is non-zero” latched status bit is set. See
Section 8.7.4.
Bit 5: Receive New Pattern Load (RNPL). A zero-to-one transition of this bit causes the programmed test pattern
(QRSS, PTS, PLF[4:0], PTF[4:0] in the
loaded into the receive pattern generator. This bit must be changed to zero and back to one for another pattern to
be loaded. Loading a new pattern forces the receive pattern generator out of the “Sync” state which causes a
resynchronization to be initiated. Note: The test pattern fields mentioned above must not change for four RCLK
cycles after this bit transitions from zero to one. See Section 8.5.1.
ADDRESS
BERT.RBCR
OFFSET
5Ch
6Ch
5Ah
5Eh
6Ah
6Eh
50h
52h
54h
56h
58h
60h
62h
64h
66h
68h
0 = Block-level update via BERT.CR:LPMU
1 = Port-level or global update as specified by PORT.CR1:PMUM
PMUM
15
—
0
7
0
registers are updated with the latest counter values and the counters are reset. This bit should
BERT.RBECR1
BERT.RBECR2
BERT.RBCR1
BERT.RBCR2
BERT.TEICR
BERT.SPR1
BERT.SPR2
BERT.SRIE
REGISTER
BERT.PCR
BERT.SRL
BERT.CR
BERT.SR
—
—
—
—
LPMU
14
—
0
6
0
BERT.CR
BERT Control Register
n * 80h + 50h
BERT Control Register
BERT Pattern Configuration Register
BERT Seed/Pattern Register 1
BERT Seed/Pattern Register 2
Transmit Error Insertion Control Register
Unused
BERT Status Register
BERT Status Register Latched
BERT Status Register Interrupt Enable
Unused
Receive Bit Error Count Register 1
Receive Bit Error Count Register 2
Receive Bit Count Register 1
Receive Bit Count Register 2
Unused
Unused
RNPL
13
—
BERT.PCR
0
5
0
REGISTER DESCRIPTION
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RPIC
12
—
register, and BSP[31:0] in the
0
4
0
MPR
11
—
0
3
0
APRD
10
—
0
2
0
DS32506/DS32508/DS32512
BERT.SPR
TNPL
—
9
0
1
0
registers) to be
BERT.RBECR
TPIC
—
8
0
0
0