DS32506W Maxim Integrated, DS32506W Datasheet - Page 40

• Manufacturer Part Number: DS32506W
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32506W

• Part # Aliases: 90-32506-W00

8.5.3.1
Errors can be inserted into the generated pattern one at a time or at a rate of one out of every 10
n is programmable (1 to 7 or off) in the BERT.TEICR:TEIR[2:0] configuration field. Single bit error insertion is
enabled by setting BERT.TEICR:BEI and can be initiated from the microprocessor interface or by the manual error
insertion pin (GPIOB2). See Section
8.6 Loopbacks
Each LIU has three internal loopbacks. See
and
(IFSEL
Analog loopback (ALB) connects the outgoing transmit signal back to the receiver’s analog front end. During ALB
the transmit signal is output normally on TXP/TXN, but the received signal on
Line loopback (LLB) connects the output of the receiver to the input of the transmitter. The LLB path does not
include the B3ZS/HDB3 decoder and encoder so that the signal looped back is exactly the same as the signal
received, including bipolar violations and code violations. During LLB, recovered clock and data are output on
RCLK, RPOS/RDAT, and RNEG/RLCV, but the TPOS/TDAT and
Diagnostic loopback (DLB) connects the TCLK, TPOS/TDAT and TNEG pins to the RCLK, RPOS/RDAT, and
RNEG/RLCV pins. During DLB (with LLB disabled), the signal on
AIS signal from the AIS generator. DLB and LLB can be enabled simultaneously to provide simultaneous remote
and local loopbacks.
8.7 Global Resources
8.7.1 Clock Rate Adapter (CLAD)
The CLAD is used to create multiple transmission-quality reference clocks from a single transmission-quality
( ± 20ppm, low jitter) clock input on the
clocks (DS3, E3, and STS-1) for use by the CDRs and jitter attenuators. Given one of these clock rates or any of
several other clock frequencies on the
internally generated reference clock signals can optionally be driven out on pins CLKA, CLKB, and
external use. In addition a fourth frequency, either 77.76MHz or 19.44MHz, can be generated and driven out on the
CLKD
When only the hardware interface is enabled
pin, and the
bypassed and powered down, and the
become inputs, and the DS3, E3, and STS-1 reference clocks, respectively, are sourced from these pins.
Transmission-quality clocks ( ± 20ppm, low jitter) must be provided to these pins for each line rate required by the
LIUs. When
77.76MHz clocks are always output on CLKA, CLKB,
When a microprocessor interface is enabled
set by the GLOBAL.CR2:CLAD[6:4] bits, as shown in
bypassed and powered down, and the
become inputs, and the DS3, E3, and STS-1 reference clocks, respectively, are sourced from these pins.
Transmission-quality clocks ( ± 20ppm, low jitter) must be provided to these pins for each line rate required by the
LIUs. CLAD[6:4] = 000 is equivalent to pulling the
enabled as needed to generate the required clocks, as determined by the CLAD[6:0] bits and the LIU mode bits
(PORT.CR2:LM[1:0]). If a clock rate is not required as a reference clock, then the PLL used to generate that clock
is automatically disabled and powered down. The CLAD[3:0] bits are output enable controls for CLKA, CLKB,
CLKC
CLKD pin (77.76MHz or 19.44MHz). Status register
CLKB
Each LIU block indicates the absence of the reference clock it requires by setting its LIU.SR:LOMC bit.
HW
and
pin for use in Telecom Bus applications.
and CLKD, respectively. Configuration bit GLOBAL.CR2:CLKD19 specifies the frequency to be output on the
≠ 000), loopbacks are controlled by the LB[1:0] and LBS fields in the
= 1), loopbacks are controlled by the
Transmit Error Insertion
CLKC
REFCLK
CLADBYP
pins and lock status for the CLAD.
frequency is fixed at 19.44MHz. When the
is low, all four PLLs in the CLAD are enabled, and the generated DS3, E3, STS-1, and
8.7.5
REFCLK
REFCLK
REFCLK
REFCLK
for more information about manual error insertion.
Figure
(IFSEL
(IFSEL
LBn[1:0]
pin. The LIUs in the device need up to three different reference
pin, the CLAD can generate all three LIU reference clocks. The
CLADBYP
pin is ignored. In this mode the CLKA, CLKB, and
pin is ignored. In this mode the CLKA, CLKB, and
2-1. When only the hardware interface is enabled
GLOBAL.SRL
≠ 000), the CLAD clock mode and the
40 of 130
= 000 and
CLKC
Table
and
8-11. When CLAD[6:4] = 000, all PLLs in the CLAD are
LBS
and CLKD, respectively.
pin high. When CLAD[6:4] ≠ 000, the PLL circuits are
HW
pins. When a microprocessor interface is enabled
TNEG
TXP/TXN
CLADBYP
provides activity status for the
= 1), the CLAD is controlled by the
pins are ignored.
can be the normal transmit signal or an
PORT.CR3
RXP/RXN
pin is high all PLLs in the CLAD are
DS32506/DS32508/DS32512
is ignored.
register.
REFCLK
n
bits. The value of
REFCLK,
frequency are
(IFSEL
CLKC
CLKC
CLADBYP
CLKC
CLKA,
= 000
pins
pins
for