DS32506W Maxim Integrated, DS32506W Datasheet - Page 13

• Manufacturer Part Number: DS32506W
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32506W

• Part # Aliases: 90-32506-W00

DS32506/DS32508/DS32512
6. CONTROL INTERFACE MODES
The DS325xx devices can be controlled by hardware interface, by microprocessor interface, or by a combination of
both interfaces at the same time. The hardware interface is configured (enabled or disabled) independently from
the microprocessor interface (8-bit parallel, 16-bit parallel, SPI, or disabled).
When the hardware interface is enabled
(HW
= 1), device configuration can be controlled by input pins, while
device status can be sensed on output pins. When the hardware interface is disabled
(HW
= 0), all the pins in
Table 7-5
are disabled (inputs are ignored; outputs are placed in a high-impedance state).
The microprocessor interface provides access to features, configuration options, and device status information that
the hardware interface does not support. The microprocessor interface is enabled and configured by the
IFSEL
pins. When IFSEL = 01X, the SPI serial interface is enabled. When IFSEL = 10X, the 8-bit parallel interface is
enabled. When IFSEL = 11X, the 16-bit parallel interface is enabled. For both the 8- and 16-bit parallel interfaces,
IFSEL[0] = 0 specifies an Intel-style bus (CS, RD, and
WR
control signals) while IFSEL[0] = 1 specifies a Motorola-
DS
style bus (CS,
, and
control signals). Through the microprocessor interface an external microprocessor can
R/W
access a set of internal configuration and status registers inside the device. Pins that are not used by the selected
microprocessor interface type but are used in other microprocessor interface modes are disabled (inputs are
ignored and considered to be low and can be left floating or wired low or high; outputs are placed in a high-
impedance state and can be left unconnected or wired low or high). When no microprocessor interface is selected
(IFSEL = 000) all microprocessor interface inputs are ignored, and all microprocessor interface outputs are put in a
high impedance state.
When both the hardware interface and the microprocessor interface are enabled at the same time, many internal
settings of the device can be configured by both a hardware interface pin and a microprocessor interface register
bit with identical names and functions. In this situation the actual internal device setting is the logical OR of pin
assertion and register bit assertion. For example, the transmitter output driver is enabled when the TOE pin is high
OR the TOE register bit is high. When both the hardware interface and the microprocessor interface are enabled at
the same time, the following hardware interface pins are ignored and replaced by equivalent configuration register
fields: LMn[1:0], JAS[1:0], JAD[1:0], LBn[1:0], and LBS.
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