DS32506W Maxim Integrated, DS32506W Datasheet - Page 53

• Manufacturer Part Number: DS32506W
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32506W

• Part # Aliases: 90-32506-W00

Bit 3: Global Performance Monitor Register Update (GPMU). When GLOBAL.CR1:GPM[1:0] = 00, this bit is
used to update all of the performance monitor registers where block-level PMUM = 1 and PORT.CR1:PMUM = 1.
When this bit transitions from low to high, all configured performance monitoring registers are updated with the
latest counter value, and all associated counters are reset. This bit should remain high until the performance
monitor update status bit (GLOBAL.SR:GPMS) goes high, and then it should be brought back low, which clears the
GPMS status bit. If a counter increment occurs at the exact same time as the counter reset, the counter is loaded
with a value of one, and the “counter is non-zero” latched status bit is set. See Section 8.7.4.
Bit 1: Reset Data Path (RSTDP). When this bit is set, it forces all of the internal data path and status registers in
all ports to their default state. This bit must be set high for a minimum of 100ns. See Section
Bit 0: Reset (RST). When this bit is set, all of the internal data path and status and control registers (except this
RST bit), on all of the ports, are reset to their default state. This bit must be set high for a minimum of 100ns. This
bit is logically ORed with the inverted hardware signal
0 = Normal operation
1 = Force all data path registers to their default values
0 = Normal operation
1 = Force all internal registers to their default values
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RST
. See Section 8.11.
DS32506/DS32508/DS32512
8.11.