DS32506W Maxim Integrated, DS32506W Datasheet - Page 68

• Manufacturer Part Number: DS32506W
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32506W

• Part # Aliases: 90-32506-W00

Bit 0: Performance Monitoring Update Status (PMS). This bit is set when the PMS bits are set in all of the port
functional blocks that are configured for port-level update control (i.e., all blocks that have PMUM = 1). Blocks that
have PMUM = 0 have no effect on this bit. In port-level software update mode, the port update request bit
(PORT.CR1:PMU) should be held high until this status bit goes high. See Section 8.7.4.
Bit 8: Transmit Clock Activity Status Latched (TCLKL). This bit is set when the signal on the TCLK pin used by
this port (TCLK n when TCC = 0, TCLK1 when TCC = 1) is active. When set, this bit causes an interrupt if interrupt
enables PORT.SRIE:TCLKIE, PORT.ISRIE:PSRIE, and GLOBAL.ISRIE: PnISRIE are all set.
Bit 0: Performance Monitoring Update Status Latched (PMSL). This bit is set when the PORT.SR:PMS status
bit changes from low to high. When set, this bit causes an interrupt if interrupt enables PORT.SRIE:PMSIE,
PORT.ISRIE:PSRIE and GLOBAL.ISRIE:PnISRIE are all set. See Section 8.7.4.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
0 = The associated update request signal is low or not all register updates are completed.
1 = The requested performance register updates are all completed.
15
—
15
—
—
—
—
—
7
7
14
14
—
—
—
—
—
—
6
6
PORT.SR
Port Status Register
n * 80h + 18h
PORT.SRL
Port Status Register Latched
n * 80h + 1Ah
13
13
—
—
—
—
—
—
5
5
68 of 130
12
12
—
—
—
—
—
—
4
4
11
11
—
—
—
—
—
—
3
3
10
10
—
—
—
—
—
—
2
2
DS32506/DS32508/DS32512
—
—
—
—
—
—
9
1
9
1
TCLKL
PMSL
PMS
—
—
8
0
0
8
0