73S1217F-68MR/F/PE Maxim Integrated, 73S1217F-68MR/F/PE Datasheet - Page 97
73S1217F-68MR/F/PE
Manufacturer Part Number
73S1217F-68MR/F/PE
Description
8-bit Microcontrollers - MCU
Manufacturer
Maxim Integrated
Datasheet
1.73S1217F-68MRFPE.pdf
(140 pages)
Specifications of 73S1217F-68MR/F/PE
Rohs
yes
Core
80515
Data Bus Width
8 bit
Part # Aliases
90-W1217+TF5
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This register is used to monitor reception of data from the smart card.
SRX Control/Status Register (SRXCtl): 0xFE08
Rev. 1.2
SRXCtl.7
SRXCtl.6
SRXCtl.5
SRXCtl.4
SRXCtl.3
SRXCtl.2
SRXCtl.1
SRXCtl.0
Bit
MSB
BIT9DAT
CRCERR
RXOVRR
PARITYE
RXEMTY
BIT9DAT
LASTRX
RXFULL
Symbol
–
–
Bit 9 Data – When in sync mode and with MODE9/8B set, this bit will contain
the data on IO (or SIO) pin that was sampled on the ninth CLK (or SCLK)
rising edge. This is used to read data in synchronous 9-bit formats.
Last RX Byte – User sets this bit during the reception of the last byte. When
byte is received and this bit is set, logic checks CRC to match 0x1D0F (T=1
mode) or LRC to match 00h (T=1 mode), otherwise a CRC or LRC error is
asserted.
(Read only) 1 = CRC (or LRC) error has been detected.
(Read only) RX FIFO is full. Status bit to indicate RX FIFO is full.
(Read only) RX FIFO is empty. This is only a status bit and does not
generate an RX interrupt.
RX Overrun – (Read Only) Asserted when a receive-over-run condition has
occurred. An over-run is defined as a byte was received from the smart
card when the RX FIFO was full. Invalid data may be in the receive FIFO.
Firmware should take appropriate action. Cleared when read. Additional
writes to the RX FIFO are discarded when a RXOVRR occurs until the
overrun condition is cleared. Will generate an RXERR interrupt.
Parity Error – (Read only) 1 = The logic detected a parity error on incoming
data from the smart card. Cleared when read. Will generate RXERR
interrupt.
LASTRX
Table 87: The SRXCtl Register
CRCERR
0x00
RXFULL
Function
RXEMTY
RXOVR
R
PARITYE
LSB
97
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