73S1217F-68MR/F/PE Maxim Integrated, 73S1217F-68MR/F/PE Datasheet - Page 105

• Manufacturer Part Number: 73S1217F-68MR/F/PE
• Description: 8-bit Microcontrollers - MCU
• Manufacturer: Maxim Integrated

Specifications of 73S1217F-68MR/F/PE

• Rohs: yes
• Core: 80515
• Data Bus Width: 8 bit
• Part # Aliases: 90-W1217+TF5

Byte Control Register (SByteCtl): 0xFE12
This register controls the processing of characters and the detection of the TS byte. When receiving, a
Break is asserted at 10.5 ETU after the beginning of the start bit. Break from the card is sampled at 11
ETU.
Rev. 1.2
SByteCtl.7
SByteCtl.6
SByteCtl.5
SByteCtl.4
SByteCtl.3
SByteCtl.2
SByteCtl.1
SByteCtl.0
Bit
MSB
–
BRKDUR.1
BRKDUR.0
Symbol
DETTS
DETTS
DIRTS
–
–
–
–
DIRTS
Detect TS Byte – 1 = Next Byte is TS, 0 = Next byte is not TS. When
set, the hardware will treat the next character received as the TS and
determine if direct or indirect convention is being used. Direct
convention is the default used if firmware does not set this bit prior to
transmission of TS by the smart card to the firmware. The hardware will
check parity and generate a break as defined by the DISPAR and
BRKGEN bits in the parity control register. This bit is cleared by
hardware after TS is received. TS is decoded before being stored in
the receive FIFO.
Direct Mode TS Select – 1 = direct mode, 0 = indirect mode.
Set/cleared by hardware when TS is processed indicating either
direct/indirect mode of operation. When switching between smart
cards, the firmware should write the bit appropriately since this register
is not unique to an individual smart card (firmware should keep track of
this bit).
Break Duration Select – 00 = 1 ETU, 01 = 1.5 ETU, 10 = 2 ETU, 11 =
reserved. Determines the length of a Break signal which is generated
when detecting a parity error on a character reception in T=0 mode.
Table 96: The SByteCtl Register
BRKDUR.1
0x2C
BRKDUR.
0
Function
–
–
–
LSB
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