73S1217F-68MR/F/PE Maxim Integrated, 73S1217F-68MR/F/PE Datasheet - Page 27
![no-image](/images/no-image-200.jpg)
73S1217F-68MR/F/PE
Manufacturer Part Number
73S1217F-68MR/F/PE
Description
8-bit Microcontrollers - MCU
Manufacturer
Maxim Integrated
Datasheet
1.73S1217F-68MRFPE.pdf
(140 pages)
Specifications of 73S1217F-68MR/F/PE
Rohs
yes
Core
80515
Data Bus Width
8 bit
Part # Aliases
90-W1217+TF5
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V
If V
used internally by the smart card electrical interface circuit and is regulated to the desired smart card
supply V
The ON_OFF pin should be connected to an SPST switch to ground. If the circuit is OFF and the switch
is closed for a de-bounce period of 50-100ms, the circuit will go into the “ON” state wherein all functions
are operating in normal fashion. If the circuit is in the “ON” state and the ON_OFF pin is connected to
ground for a period greater than the de-bounce period, OFF_REQ will be asserted high and held
regardless of the state of ON/OFF. The OFF_REQ signal should be connected to one of the interrupt
pins to signal the CPU core that a request to shutdown has been initiated. The firmware will
V
maximum).
V
of 4.0 to 6.5 volts.
V
(break-before-make). They will not be enabled at the same time. V
V
The power that is supplied to the V
up-converted to the intermediate voltage V
inductor (nominal value = 10 μH) must be connected from V
capacitor must be connected to V
V
V
68 and must be directly tied to all other V
digital logic, input/output buffering, and analog functions. It can also be used for external circuitry: Up to
20mA current can be supplied to external devices simultaneously to the 73S1217F’s digital core
maximum consumption.
1.7.3
The 73S1217F features an ON_OFF input pin for a momentary contract, main-system ON/OFF switch.
The purpose of this switch is to place the circuit in a very low-power mode – the “OFF” mode – where the
digital core of the circuit is no longer powered, therefore allowing the lowest possible current
consumption.
When in “OFF” mode, an action on the ON/OFF switch will turn-on the power supply of the digital core
(V
requires firmware action.
When in “ON” mode, an action on the ON/OFF switch will send a request to the controller that will have to
be acknowledged (firmware action required) in order to enter the “OFF” state.
When placed into the “OFF” state, the 73S1217F will consume minimum current from V
and V
When in “ON” mode, the 73S1217F will operate normally, with all the features described in this document
available. V
Whenever V
ON/OFF switch and circuitry are overridden and the 73S1217F is in the “ON” state with V
available.
Without V
Rev. 1.2
BUS
BAT
BAT
BAT
PC
P
P
DD
requires a 4.7μF filter capacitor and will have a nominal value of 5.5V during normal operation. V
is also used internally to generate a 3.3V nominal, regulated power supply V
PC
pin to prevent current flow from V
) and apply a power-on-reset condition. Alternatively, entering the “OFF” mode from the “ON” mode
is expected to be supplied from a battery of three to four series connected cells with a voltage value
and V
when V
is typically supplied by an external power supply and ranges in value from 4.4 to 5.5 volts (6.5V
DD
is provided and either V
Power ON/OFF
CC
will be unavailable (V
BUS
BUS
voltage (can be programmed for values of 5V, 3V, or 1.8V).
P
BUS
BUS
applied, the circuit is by default in the “OFF” state, and will respond only to the ON_OFF pin.
and V
are internally switched to V
power is supplied, the circuit will be automatically in the “ON” state: The functions of the
is present (i.e. V
DD
will be available (V
BAT
DD
BUS
out = 0V and V
or V
PC
PC
.
always has the priority).
BUS
BAT
pin (externally or internally, i.e. through V
or V
DD
is also used, the source of V
DD
PC
P
pins on the 73S1217F (pins 28 and 40). V
out = 3.3V and V
by two separate FET switches configured as a SPDT switch
utilizing an inductive, step-up converter. A series power
BUS
P
into the V
= 0V).
PC
PC
source.
P
to the pin LIN, and a 10μF low ESR filter
= 5.5V nominal).
BUS
PC
is automatically selected in lieu of
must be diode isolated from the
BAT
DD
. V
or V
DD
BUS
DD
PC
is output on pin
powers all the
P
– see above) is
and V
and V
BAT
DD
; V
P
P
is
27
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