73S1217F-68MR/F/PE Maxim Integrated, 73S1217F-68MR/F/PE Datasheet - Page 54
73S1217F-68MR/F/PE
Manufacturer Part Number
73S1217F-68MR/F/PE
Description
8-bit Microcontrollers - MCU
Manufacturer
Maxim Integrated
Datasheet
1.73S1217F-68MRFPE.pdf
(140 pages)
Specifications of 73S1217F-68MR/F/PE
Rohs
yes
Core
80515
Data Bus Width
8 bit
Part # Aliases
90-W1217+TF5
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1.7.10 Real-Time Clock with Hardware Watchdog (RTC)
Figure 10 shows the block diagram of the Real Time Clock. The RTC block uses the 32768Hz oscillator
signal and divider logic to produce 0.5-second time marks. The time marks are used to create interrupts
at intervals from 0.5 seconds to 8 seconds as selected by RTC Interval (RTCINV(2:0)). The 32768Hz
oscillator can be disabled but is intended to operate at all times and in all power consumption modes.
If a 32kHz crystal is not provided, the 32 kHz oscillator should be disabled and the RTC will operate from
MCLK (96MHz) divided by 2930 (refer to the oscillator and clock generation section). The clock
generated by the high speed oscillator will not yield exactly 32768 Hz, but a frequency of approximately
32764.505119 Hz. This yields a negative 106.6 PPM (1 / 9375) error with respect to 32768Hz. The RTC
circuit provides hardware to compensate for this error by providing an offset circuit that will adjust the
RTC counter.
54
RTCCLK
R/W BUS
R/W BUS
ADVANCE
IF
IF
Figure 10: Real Time Clock Block Diagram
overflow* sign=0, extra count
overflow* sign=1, skip one count
DIVIDER
24 BIT ACCUMULATOR
23 BIT TRIM VALUE
1/2 Second
1 Second
4 Second
2 Second
8 Second
ADDER
32 BIT COUNTER
1/2
1/2
1
2
4
8
1
2
OVERFLOW
INTERRUPT
SELECT
SELECT
COUNT
RATE
RATE
SIGN
START
R/W BUS
RTC INT
1/2s TIMEOUT
WATCH
TIMER
DOG
RESET
WDT_TIMEOUT
1.024KHz
CLOCK
RTC ISR
Rev. 1.2
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