CY7C68034-56LTXI Cypress Semiconductor, CY7C68034-56LTXI Datasheet - Page 9

• Manufacturer Part Number: CY7C68034-56LTXI
• Description: USB Interface IC EZ-USB NX2LP-Flex Flash Controller
• Manufacturer: Cypress Semiconductor

Specifications of CY7C68034-56LTXI

• Rohs: yes
• Product: USB 2.0
• Data Rate: 96 Mbps
• Interface Type: I2C
• Operating Supply Voltage: 3.3 V
• Operating Supply Current: 43 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-56
• Minimum Operating Temperature: - 40 C

Table 4. Individual FIFO/GPIF Interrupt Sources
If autovectoring is enabled (AV4EN = 1 in the INTSET-UP
register), the NX2LP-Flex substitutes its INT4VEC byte.
Therefore, if the high byte (‘page’) of a jump-table address is
preloaded at location 0x554, the automatically inserted
INT4VEC byte at 0x555 directs the jump to the correct address
out of the 14 addresses within the page. When the ISR occurs,
the NX2LP-Flex pushes the program counter to its stack and
then jumps to address 0x553; it expects to find a ‘jump’
instruction to the ISR Interrupt service routine here.
Reset and Wakeup
Reset Pin
The input pin RESET#, resets the NX2LP-Flex when asserted.
This pin has hysteresis and is active LOW. When a crystal is
Document Number: 001-04247 Rev. *J
Note
1. If the external clock is powered at the same time as the CY7C68033/CY7C68034 and has a stabilization wait period, it must be added to the 200 s.
RESET#
Priority
V
CC
10
12
13
14
11
1
2
3
4
5
6
7
8
9
INT4VEC Value
0x5AC
T
0x58C
0x59C
0x5A0
0x5A4
0x5A8
0x580
0x588
0x590
0x594
0x598
0x5B0
0x5B4
Power-on Reset
0x584
RESET
GPIFDONE
GPIFWF
Figure 5. Reset Timing Plots
Source
EP2PF
EP4PF
EP6PF
EP8PF
EP2EF
EP4EF
EP6EF
EP8EF
EP2FF
EP4FF
EP6FF
EP8FF
V
3.3 V
3.0 V
0 V
IL
RESET#
V
Endpoint 2 programmable flag
Endpoint 4 programmable flag
Endpoint 6 programmable flag
Endpoint 8 programmable flag
Endpoint 2 empty flag
Endpoint 4 empty flag
Endpoint 6 empty flag
Endpoint 8 empty flag
Endpoint 2 full flag
Endpoint 4 full flag
Endpoint 6 full flag
Endpoint 8 full flag
GPIF operation complete
GPIF waveform
used as the clock source for the NX2LP-Flex, the reset period
must enable the stabilization of the crystal and the PLL. This
reset period should be approximately 5 ms after V
reached 3.0V. If the crystal input pin is driven by a clock signal,
the internal PLL stabilizes in 200 s after V
3.0 V
during operation. A POR is defined as the time reset is asserted
while power is being applied to the circuit. A powered reset is
defined to be when the NX2LP-Flex has previously been
powered on and operating and the RESET# pin is asserted.
For more information on power on reset implementation for the
EZ-USB family of products, refer to the application note
EZ-USB FX2™/AT2™/SX2™.
CC
[1]
.
Figure 5
T
shows a POR condition and a reset applied
RESET
Powered Reset
CY7C68033/CY7C68034
Notes
V
3.3 V
0 V
IL
CC
has reached
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CC
has