CY7C68034-56LTXI Cypress Semiconductor, CY7C68034-56LTXI Datasheet - Page 17

• Manufacturer Part Number: CY7C68034-56LTXI
• Description: USB Interface IC EZ-USB NX2LP-Flex Flash Controller
• Manufacturer: Cypress Semiconductor

Specifications of CY7C68034-56LTXI

• Rohs: yes
• Product: USB 2.0
• Data Rate: 96 Mbps
• Interface Type: I2C
• Operating Supply Voltage: 3.3 V
• Operating Supply Current: 43 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-56
• Minimum Operating Temperature: - 40 C

Table 8. NX2LP-Flex Pin Descriptions
Document Number: 001-04247 Rev. *J
QFN Pin
Note
Number
6. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power up and in
56-pin
42
54
29
30
31
standby. Note also that no pins should be driven while the device is powered down.
9
8
5
4
1
2
DMINUS
DPLUS
RESET#
XTALIN
XTALOUT
GPIO9
RDY0 or SLRD
RDY1 or SLWR
CTL0 or
FLAGA
CTL1 or
FLAGB
CTL2 or
FLAGC
Default Pin
Name
Firmware
Usage
GPIO9
R_B1#
R_B2#
NAND
RE0#
RE1#
WE#
N/A
N/A
N/A
N/A
N/A
[6]
Output
Type
I/O/Z
I/O/Z
Input
Input
Input
Input
O/Z
O/Z
O/Z
O/Z
Pin
Default
12 MHz GPIO9 is a bidirectional I/O port pin.
State
N/A
N/A
N/A
N/A
N/A
H
H
H
Z
Z
USB D– Signal. Connect to the USB D– signal.
USB D+ Signal. Connect to the USB D+ signal.
Active LOW Reset. Resets the entire chip. See section
Wakeup on page 9
Crystal Input. Connect this signal to a 24 MHz parallel-resonant,
fundamental mode crystal and load capacitor to GND.
It is also correct to drive XTALIN with an external 24 MHz square
wave derived from another clock source. When driving from an
external source, the driving signal should be a 3.3 V square wave.
Crystal Output. Connect this signal to a 24 MHz parallel-resonant,
fundamental mode crystal and load capacitor to GND.
If an external clock is used to drive XTALIN, leave this pin open.
Multiplexed pin whose function is selected by IFCONFIG[1:0].
RDY0 is a GPIF input signal.
SLRD is the input-only read strobe with programmable polarity
(FIFOPINPOLAR[3]) for the slave FIFOs connected to FD[7:0] or
FD[15:0].
R_B1# is a NAND Ready/Busy input signal.
Multiplexed pin whose function is selected by IFCONFIG[1:0].
RDY1 is a GPIF input signal.
SLWR is the input-only write strobe with programmable polarity
(FIFOPINPOLAR[2]) for the slave FIFOs connected to FD[7:0] or
FD[15:0].
R_B2# is a NAND Ready/Busy input signal.
Multiplexed pin whose function is selected by IFCONFIG[1:0].
CTL0 is a GPIF control output.
FLAGA is a programmable slave-FIFO output status flag signal.
Defaults to programmable for the FIFO selected by the
FIFOADR[1:0] pins.
WE# is the NAND write enable output signal.
Multiplexed pin whose function is selected by IFCONFIG[1:0].
CTL1 is a GPIF control output.
FLAGB is a programmable slave-FIFO output status flag signal.
Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins.
RE0# is a NAND read enable output signal.
Multiplexed pin whose function is selected by IFCONFIG[1:0].
CTL2 is a GPIF control output.
FLAGC is a programmable slave-FIFO output status flag signal.
Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins.
RE1# is a NAND read enable output signal.
for more details.
Description
CY7C68033/CY7C68034
Page 17 of 40
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