MAX98090BEWJ+T Maxim Integrated, MAX98090BEWJ+T Datasheet - Page 85

• Manufacturer Part Number: MAX98090BEWJ+T
• Description: Interface - CODECs 5V 130mW Stereo Headphone Amp
• Manufacturer: Maxim Integrated

MAX98090
Table 11. Microphone Bias Level Configuration Register
Table 12. Digital Microphone Clocks for Commonly Used Master Clocks Settings
Table 13. Digital Microphone Enable
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BIT
BIT
Frequency (f
Master Clock Frequency (f
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Approximate Digital
Microphone Clock
MBVSEL[1:0]
MICCLK[2:0]
DIGMICR
DIGMICL
ADDRESS: 0x12
ADDRESS: 0x13
NAME
NAME
DMICCLK
—
—
—
—
—
—
—
—
—
)
TYPE
f
f
f
f
f
f
TYPE
R/W
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
R/W
R/W
R/W
MCLK
—
—
—
—
—
—
—
—
—
/2
/3
/4
/5
/6
/8
)
POR
POR
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
3.333MHz
1.667MHz
1.25MHz
5.0MHz
2.5MHz
2.0MHz
10MHz
Microphone Bias Level Configuration
Digital Microphone Clock Rate Configuration
Digital Microphone Right Channel Enable
Digital Microphone Left Channel Enable
00: 2.2V
01: 2.4V
000: f
001: f
010: f
011: f
0: Right record channel uses on-chip ADC.
1: Right record channel uses digital microphone input.
0: Left record channel uses on-chip ADC.
1: Left record channel uses digital microphone input.
DMICCLK
DMICCLK
DMICCLK
DMICCLK
11.2896MHz
5.645MHz
3.763MHz
2.822MHz
2.258MHz
1.882MHz
1.411MHz
= f
= f
= f
= f
PCLK
PCLK
PCLK
PCLK
/5
/2
/3
/4
Ultra-Low Power Stereo Audio Codec
6.0MHz
4.0MHz
3.0MHz
2.4MHz
2.0MHz
1.5MHz
12MHz
DESCRIPTION
DESCRIPTION
—
—
—
—
—
—
—
—
—
12.288MHz
10: 2.55V
11: 2.8V
100: f
101: f
110: Reserved
111: Reserved
6.144MHz
4.096MHz
3.072MHz
2.458MHz
2.048MHz
1.536MHz
DMICCLK
DMICCLK
= f
= f
13/26MHz
4.333MHz
2.167MHz
1.625MHz
3.25MHz
6.5MHz
2.6MHz
PCLK
PCLK
Maxim Integrated │ 85
/6
/8
19.2MHz
3.84MHz
6.4MHz
4.8MHz
3.2MHz
2.4MHz
—