MAX98090BEWJ+T Maxim Integrated, MAX98090BEWJ+T Datasheet - Page 105

• Manufacturer Part Number: MAX98090BEWJ+T
• Description: Interface - CODECs 5V 130mW Stereo Headphone Amp
• Manufacturer: Maxim Integrated

MAX98090
When FREQ[3:0] register is set to 0 (FREQ[3:0] = 0000),
exact integer mode is disabled. When the MSB is set to 1
(FREQ[3:0] = 1XXX) exact integer mode is enabled and
the remaining bits determine which setting is selected
(Table 39). If exact integer mode is enabled, the manual
ratio mode settings (Tables 33 to 36) are preserved but
ignored. However, if this mode is later disabled, the
manual ratio mode settings reassert.
Manual Ratio Mode
In manual ratio mode, the NI and MI registers (Table 40
to Table 43) are directly programmed to set up the clock
ratio. Manual ratio mode is only active when the quick
Configuration and Exact Integer Modes are disabled. In
manual ratio mode, if USE_MI (Table 39) is set to 0, MI
is fixed at its maximum value of 0xFFFF (65536) and
the programmed value has no effect. For optimal perfor-
mance (especially with any noninteger PCLK to LRCLK
ratio), set USE_MI to 1 and calculate both MI and NI.
To calculate the appropriate NI and MI value, use the fol-
lowing method:
1) Choose the over sampling rate (OSR). If f
2) Calculate the oversampling frequency using the
Table 40. Manual Clock Ratio Configuration Register (NI MSB)
www.maximintegrated.com
BIT
7
6
5
4
3
2
1
0
x f
OSR can be set to either 128 or 64. For optimal per-
formance, choose OSR = 128 when possible.
LRCLK frequency, and the selected oversampling rate:
LRCLK
ADDRESS: 0x1D
NI[14:8]
, then OSR must be set to 64. Otherwise,
NAME
—
f
OSR
= f
LRCLK
TYPE POR
R/W
—
x OSR.
—
0
0
0
0
0
0
0
Upper half of the PLL N value used in master mode clock generation
to calculate the frequency ratio (manual ratio master mode).
PCLK
< 256
3) Calculate MI using the prescaled master clock fre-
4) Calculate NI using the calculated oversampling fre-
Slave Mode Clock Configuration
When the device is configured as a digital audio slave, the
frame clock (LRCLK) and bit clock (BCLK) are configured
as external inputs. These inputs accept an externally
generated frame and bit clock, and then an internal PLL
determines the correct PCLK to LRCLK frequency ratio.
Within a few LRCLK cycles, the internal PLL is locked
onto the clock ratio and then automatically programs the
internal divider ratio appropriately.
In slave mode, the clock generation register settings have
no effect (quick configuration, exact integer, and manual
ratio mode settings have no effect). The correct MCLK to
PCLK scaling factor, mode (voice/audio), and oversam-
pling rate still need to be programmed. However, all other
clock configuration settings are for master mode only. The
only exception to this is when the digital audio format is
set to slave mode operation with right justified data. In
this configuration, the BCLK setting (BSEL[2:0], Table 29)
is used to determine the number of leading padding bits
(BCLK cycles) to insert (skip) before the data transmis-
sion/receiving in each frame.
Ultra-Low Power Stereo Audio Codec
quency, and the greatest common denominator (GCD)
of the prescaled master clock frequency and the cal-
culated oversampling frequency:
quency and MI value:
DESCRIPTION
MI = f
—
NI = f
PCLK /
OSR
GCD(f
x MI/f
PCLK
PCLK
Maxim Integrated │ 105
, f
OSR
)