MAX98090BEWJ+T Maxim Integrated, MAX98090BEWJ+T Datasheet - Page 70

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MAX98090BEWJ+T

Manufacturer Part Number
MAX98090BEWJ+T
Description
Interface - CODECs 5V 130mW Stereo Headphone Amp
Manufacturer
Maxim Integrated
Datasheet
MAX98090
Table 1. MAX98090 Control Register Map (continued)
www.maximintegrated.com
ADDR
ADC PATH AND CONFIGURATION REGISTERS
CLOCK CONFIGURATION REGISTERS
INTERFACE CONTROL REGISTERS
0x1A RECORD SIDETONE R/W
0x1B
0x1C
0x1D
0x1E
0x1F
0x15 LEFT ADC MIXER R/W
0x16 RIGHT ADC MIXER R/W
0x17
0x18
0x19
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
REGISTER DESCRIPTION
RECORD BIQUAD
CONFIGURATION
CONFIGURATION
SYSTEM CLOCK R/W
RIGHT RECORD
MASTER MODE
TDM CONTROL
DAI PLAYBACK
LEFT RECORD
EQ PLAYBACK
CLOCK MODE
CLOCK RATIO
CLOCK RATIO
CLOCK RATIO
CLOCK RATIO
TDM FORMAT
INTERFACE
FORMAT
NI MSB
MI MSB
MI LSB
FILTER
NI LSB
LEVEL
LEVEL
LEVEL
LEVEL
LEVEL
NAME
I/O
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MODE
BIT 7
MAS
DVM
SLOTL[1:0]
DSTS[1:0]
AHPF
BIT 6
FREQ[3:0]
AVRG[2:0]
AVLG[2:0]
DHPF
BIT 5
LTEN
RJ
SLOTR[1:0]
PSCLK[1:0]
DVG[1:0]
REGISTER CONTENTS
EQCLP
LBEN
BIT 4
DHF
WCI
MI[15:8]
Ultra-Low Power Stereo Audio Codec
MI[7:0]
NI[7:0]
MIXADR[6:0]
MIXADL[6:0]
DMONO
NI[14:8]
BIT 3
BCI
DVST[4:0]
HIZOFF
BIT 2
DLY
SLOTDLY[3:0]
DVEQ[3:0]
AVBQ[3:0]
AVR[3:0]
AVL[3:0]
DV[3:0]
BSEL[2:0]
SDOEN
BIT 1
FSW
WS[1:0]
USE_MI
Maxim Integrated │ 70
SDIEN
BIT 0
TDM
STATE
0x00
0x00
0x03
0x03
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x80
0x00
0x00
POR

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