AT25DL081-SSHN-T Adesto Technologies, AT25DL081-SSHN-T Datasheet - Page 22

• Manufacturer Part Number: AT25DL081-SSHN-T
• Description: Flash 8M 1.65-1.95V 100Mhz Serial Flash
• Manufacturer: Adesto Technologies

Specifications of AT25DL081-SSHN-T

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Flash
• Memory Size: 8 Mbit
• Architecture: Flexible, Uniform Erase
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 1.95 V
• Supply Voltage - Min: 1.65 V
• Maximum Operating Current: 20 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8

9.2
Write Disable
The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Register to the Logical 0
state. With the WEL bit reset, all Byte/Page Program, Erase, Protect Sector, Unprotect Sector, Sector Lockdown, Freeze
Sector Lockdown State, Program OTP Security Register, Write Status Register, and Write Configuration Register
commands will not be executed. Other conditions can also cause the WEL bit to be reset. For more details, refer to the
WEL bit section of the Status Register description.
To issue the Write Disable command, the CS pin must first be asserted and then the opcode 04h must be clocked into
the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be
ignored. When the CS pin is deasserted, the WEL bit in the Status Register will be reset to a Logical 0. The complete
opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even
byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not
change.
Figure 9-2. Write Disable
SCK
SO
CS
SI
MSB
High-impedance
0
0
0
1
0
2
Opcode
0
3
0
4
1
5
0
6
0
7
AT25DL081 [DATASHEET]
8732E–DFLASH–1/2013
22