W5200 WIZnet, W5200 Datasheet - Page 21

• Manufacturer Part Number: W5200
• Description: Ethernet ICs 3-IN-1 ENET CONTR TCP/IP+MAC+PHY
• Manufacturer: WIZnet
• Type: Embedded Systems using SPIr

Specifications of W5200

• Rohs: yes
• Product: Ethernet Controllers
• Data Rate: 10 Mb/s, 100 Mb/s
• Supply Voltage - Max: 3.63 V
• Supply Voltage - Min: 2.97 V
• Maximum Operating Temperature: + 85 C
• Package / Case: QFN-48
• Ethernet Connection Type: 10Base-T, 100Base-TX, PPPoE
• Maximum Power Dissipation: 528 mW
• Maximum Supply Current: 5 uA
• Minimum Operating Temperature: - 55 C
• Standard Supported: 802.3

IR2(W
IR2 is
relate
keeps
autom
© Co
Bit
S7_
7
6
5
4
3
2
1
0
W5200 SOCK
_INT
s the Registe
matically.
7
7
opyright 201
ed bit of IR2
s low until a
Symbol
S7_INT
S6_INT
S5_INT
S4_INT
S3_INT
S2_INT
S1_INT
S0_INT
S6_
_INT
KET Interrup
all bits of Sn
er to notify W
2 is set as ‘1
11WIZnet Co
6
6
l
Descri
When
interru
cleared
When
interru
cleared
When
interru
cleared
When
interru
cleared
When
interru
cleared
When
interru
cleared
When
interru
cleared
When
interru
cleared
S5_
pt Register)[
_INT
upt informat
upt informat
upt informat
upt informat
upt informat
upt informat
upt informat
upt informat
5
5
W5200 SOCK
o., Inc. All rig
d when S7_IR
d when S6_IR
d when S5_IR
d when S4_IR
d when S3_IR
d when S2_IR
d when S1_IR
d when S0_IR
_IR becomes
ption
’. When rela
an interrup
an interrup
an interrup
an interrup
an interrup
an interrup
an interrup
an interrup
S4_
KET interrupt
_INT
[R/W][0x003
4
4
pt occurs a
pt occurs a
pt occurs a
pt occurs a
pt occurs a
pt occurs a
pt occurs a
pt occurs a
s ‘0’. If all b
tion is appl
R is cleared
tion is appl
R is cleared
tion is appl
R is cleared
tion is appl
R is cleared
tion is appl
R is cleared
tion is appl
R is cleared
tion is appl
R is cleared
tion is appl
R is cleared
ghts reserve
ated Mask B
S3_
_INT
34][0x00]
at SOCKET
at SOCKET
at SOCKET
at SOCKET
at SOCKET
at SOCKET
at SOCKET
at SOCKET
ed.
bits of Sn_IR
3
3
t to the Host
lied to S7_I
lied to S6_I
lied to S5_I
lied to S4_I
lied to S3_I
lied to S2_I
lied to S1_I
lied to S0_I
it is ‘1’, nIN
to 0x00 by h
to 0x00 by h
to 0x00 by h
to 0x00 by h
to 0x00 by h
to 0x00 by h
to 0x00 by h
to 0x00 by h
S2_
NT signal is a
_INT
host.
host.
host.
host.
host.
host.
host.
host.
2
t. If any inte
2
R. This bit
R. This bit
R. This bit
R. This bit
R. This bit
R. This bit
R. This bit
R. This bit
7-th, it be
6-th, it be
5-th, it be
4-th, it be
3-th, it be
2-th, it be
1-th, it be
0-th, it be
become ‘0’
S1_
ecomes ‘1’.
ecomes ‘1’.
ecomes ‘1’.
ecomes ‘1’.
ecomes ‘1’.
ecomes ‘1’.
ecomes ‘1’.
ecomes ‘0’.
_INT
asserted low
’, it become
errupt occur
1
1
is automat
is automat
is automat
is automat
is automat
is automat
is automat
is automat
S0_
w. nINT
rs, the
_INT
0
0
s high
ically
ically
ically
ically
ically
ically
ically
ically
This
This
This
This
This
This
This
This
21