LCMXO2-1200ZE-1UWG25ITR50 Lattice, LCMXO2-1200ZE-1UWG25ITR50 Datasheet - Page 76

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LCMXO2-1200ZE-1UWG25ITR50

Manufacturer Part Number
LCMXO2-1200ZE-1UWG25ITR50
Description
FPGA - Field Programmable Gate Array 19 LUTs 19 IO 1.2V 1 Spd
Manufacturer
Lattice
Datasheet

Specifications of LCMXO2-1200ZE-1UWG25ITR50

Rohs
yes
Number Of Gates
1200
Embedded Block Ram - Ebr
64 Kbit
Number Of I/os
19
Maximum Operating Frequency
400 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 100 C
Mounting Style
SMD/SMT
Package / Case
WLCPS-25
Distributed Ram
10 Kbit
Operating Supply Current
56 uA
Switching Test Conditions
Figure 3-13 shows the output test load used for AC testing. The specific values for resistance, capacitance, volt-
age, and other test conditions are shown in Table 3-5.
Figure 3-13. Output Test Load, LVTTL and LVCMOS Standards
Table 3-5. Test Fixture Required Components, Non-Terminated Interfaces
Note: Output test conditions for all other interfaces are determined by the respective standards.
LVTTL and LVCMOS settings (L -> H, H -> L)
LVTTL and LVCMOS 3.3 (Z -> H)
LVTTL and LVCMOS 3.3 (Z -> L)
Other LVCMOS (Z -> H)
Other LVCMOS (Z -> L)
LVTTL + LVCMOS (H -> Z)
LVTTL + LVCMOS (L -> Z)
Test Condition
DUT
188
R1
V
R1
T
3-37
0pF
0pF
CL
CL
LVTTL, LVCMOS 3.3 = 1.5V
LVCMOS 2.5 = V
LVCMOS 1.8 = V
LVCMOS 1.5 = V
LVCMOS 1.2 = V
1.5
1.5
V
V
V
V
Test Poi n t
OH
OL
CCIO
CCIO
DC and Switching Characteristics
- 0.15
- 0.15
/2
/2
MachXO2 Family Data Sheet
Timing Ref.
CCIO
CCIO
CCIO
CCIO
/2
/2
/2
/2
V
V
V
V
V
V
VT
OH
OH
OH
OL
OL
OL

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