LCMXO2-1200ZE-1UWG25ITR50 Lattice, LCMXO2-1200ZE-1UWG25ITR50 Datasheet - Page 51

no-image

LCMXO2-1200ZE-1UWG25ITR50

Manufacturer Part Number
LCMXO2-1200ZE-1UWG25ITR50
Description
FPGA - Field Programmable Gate Array 19 LUTs 19 IO 1.2V 1 Spd
Manufacturer
Lattice
Datasheet

Specifications of LCMXO2-1200ZE-1UWG25ITR50

Rohs
yes
Number Of Gates
1200
Embedded Block Ram - Ebr
64 Kbit
Number Of I/os
19
Maximum Operating Frequency
400 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 100 C
Mounting Style
SMD/SMT
Package / Case
WLCPS-25
Distributed Ram
10 Kbit
Operating Supply Current
56 uA
LVPECL
The MachXO2 family supports the differential LVPECL standard through emulation. This output standard is emu-
lated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all the
devices. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Dif-
ferential LVPECL is one possible solution for point-to-point signals.
Figure 3-3. Differential LVPECL
Table 3-3. LVPECL DC Conditions
For further information on LVPECL, BLVDS and other differential interfaces please see details of additional techni-
cal documentation at the end of the data sheet.
16mA
16mA
Z
R
R
R
V
V
V
V
Z
I
1. For input buffer, see LVDS table.
DC
OUT
OH
OL
OD
BACK
T
CM
S
P
V
V
CCIO
CCIO
Symbol
On-chip
= 3.3V
= 3.3V
Output impedance
Driver series resistor
Driver parallel resistor
Receiver termination
Output high voltage
Output low voltage
Output differential voltage
Output common mode voltage
Back impedance
DC output current
Over Recommended Operating Conditions
1
Off-chip
93 ohms
93 ohms
Description
Transmission line, Zo = 100 ohm differential
196 ohms
3-12
Nominal
100.5
12.11
2.05
1.25
0.80
1.65
196
100
100 ohms
10
93
DC and Switching Characteristics
MachXO2 Family Data Sheet
Off-chip
Ohms
Ohms
Ohms
Ohms
Ohms
Units
mA
V
V
V
V
On-chip
+
-

Related parts for LCMXO2-1200ZE-1UWG25ITR50